Internal BUS design: MUX or OR-GATE?

H

Haiwen

Guest
Hello,

I have an internal BUS for all the registers in different modules. I
found it is inconvenient to build a MUX for the read BUS, instead I
want to just OR all the buses together (output 0 when deselected).

The design is for Spartan-3A FPGA, does anyone know whether there's
any difference on resource usage or performance?


Best Regards,
Haiwen
 
Haiwen <heavenfish@gmail.com> wrote:

I have an internal BUS for all the registers in different modules. I
found it is inconvenient to build a MUX for the read BUS, instead I
want to just OR all the buses together (output 0 when deselected).

The design is for Spartan-3A FPGA, does anyone know whether there's
any difference on resource usage or performance?
Click to expand...
As far as I know, if you write internal tristate logic, it generates
something similar to the OR logic you mention.

If you have enable lines, like for tristate gates, then the OR
logic should be most efficient. If you have an encoded binary
address, like for a mux select input, then the mux is probably
better.

Also, the enable/OR works better if the enable signals come from
widely spaced modules.

-- glen
 
On Mar 13, 1:06 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
Haiwen <heavenf...@gmail.com> wrote:
I have an internal BUS for all the registers in different modules. I
found it is inconvenient to build a MUX for the read BUS, instead I
want to just OR all the buses together (output 0 when deselected).
The design is for Spartan-3A FPGA, does anyone know whether there's
any difference on resource usage or performance?

As far as I know, if you write internal tristate logic, it generates
something similar to the OR logic you mention.

If you have enable lines, like for tristate gates, then the OR
logic should be most efficient. If you have an encoded binary
address, like for a mux select input, then the mux is probably
better.

Also, the enable/OR works better if the enable signals come from
widely spaced modules.

-- glen
Click to expand...
Thanks, Glen. The design was using tristate gates and let the
synthesizer to optimize it. I want the bus be 0 when it is floating
(none is selected), but it seems the Synthesizer can't assure it all
the time. So I decide to change it to OR-gates.

Haiwen
 
On Tuesday, March 13, 2012 3:32:28 AM UTC+1, Haiwen wrote:
Hello,

I have an internal BUS for all the registers in different modules. I
found it is inconvenient to build a MUX for the read BUS, instead I
want to just OR all the buses together (output 0 when deselected).

The design is for Spartan-3A FPGA, does anyone know whether there's
any difference on resource usage or performance?


Best Regards,
Haiwen
Click to expand...
If you have many bus terminals you can use the carry logic to do a fast wide OR.

Andreas
 
(snip, I wrote)
As far as I know, if you write internal tristate logic, it generates
something similar to the OR logic you mention.
Click to expand...
Haiwen <heavenfish@gmail.com> wrote:
Thanks, Glen. The design was using tristate gates and let the
synthesizer to optimize it. I want the bus be 0 when it is floating
(none is selected), but it seems the Synthesizer can't assure it all
the time. So I decide to change it to OR-gates.
Click to expand...
With tristate gates, you normally wouldn't be assured of that.

The synthesizer could do it with either OR or AND logic.

As they like to move around inverters, you probably can't count on
one or the other, even for mutliple lines on the same bus.

If you put weak pull-ups on the lines, though, and the synthesizer
knows what to do with them, then it should generate OR.

-- glen
 
Haiwen

Tristate muxes used to a good method in FPGAs prior to Spartan-3/3E/3A
because the resource existed. The internal tristates don't exist in
Spartan-3 and later so a synthesiser will attempt to convert to a
logic function anyway. It might not always get that right as you
physically can't do the tristate. Because of these uncertainies you
might get a bigger, slower, mux this way.

A logic mux is the way that OPB/PLB buses have worked and those worked
by anding '1' when enabled with a given mux input. The speed and size
of the mux will depend on the number of inputs and the data width. For
speed you can often pipeline this sort of mux with registers and get a
clocking speed increase at the penalty of extra latency.

John Adair
Enterpoint Ltd. - Home of Drigmorn2. The Spartan-3A Development Board.


On Mar 13, 2:32 am, Haiwen <heavenf...@gmail.com> wrote:
Hello,

I have an internal BUS for all the registers in different modules. I
found it is inconvenient to build a MUX for the read BUS, instead I
want to just OR all the buses together (output 0 when deselected).

The design is for Spartan-3A FPGA, does anyone know whether there's
any difference on resource usage or performance?

Best Regards,
Haiwen
Click to expand...
 
John Adair <g1@enterpoint.co.uk> wrote:

Tristate muxes used to a good method in FPGAs prior to Spartan-3/3E/3A
because the resource existed. The internal tristates don't exist in
Spartan-3 and later so a synthesiser will attempt to convert to a
logic function anyway. It might not always get that right as you
physically can't do the tristate. Because of these uncertainies you
might get a bigger, slower, mux this way.
Click to expand...
It really doesn't make sense to generate an actual MUX, as that
would require a preceding priority encoder.

Two that are more obvious are AND/OR logic and OR/AND logic,
the former gives zero with no enables, the latter one.
(OR/AND uses active low enables. The synthsizer can always add
inverters where needed.)

Assuming the synthesizer knows about them, weak pull-ups should
generate the former, and weak pull-downs the latter.

If you do know that the synthesizer will generate one of those, does
it make more sense to rewrite the logic using one, or just leave it
as is?

-- glen
 
On Mar 16, 2:57 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
John Adair <g...@enterpoint.co.uk> wrote:
Tristate muxes used to a good method in FPGAs prior to Spartan-3/3E/3A
because the resource existed. The internal tristates don't exist in
Spartan-3 and later so a synthesiser will attempt to convert to a
logic function anyway. It might not always get that right as you
physically can't do the tristate. Because of these uncertainies you
might get a bigger, slower, mux this way.

It really doesn't make sense to generate an actual MUX, as that
would require a preceding priority encoder.

Two that are more obvious are AND/OR logic and OR/AND logic,
the former gives zero with no enables, the latter one.
(OR/AND uses active low enables. The synthsizer can always add
inverters where needed.)

Assuming the synthesizer knows about them, weak pull-ups should
generate the former, and weak pull-downs the latter.

If you do know that the synthesizer will generate one of those, does
it make more sense to rewrite the logic using one, or just leave it
as is?

-- glen
Click to expand...
I actually is using weak pull-down for my test bench to get right RTL
simulation results. I'm not aware that this can also direct
Synthesizer's results, I thought the weak pull-down buffers are not
recognized by Synthesizers. I'll give it a try to see whether it
works, then I don't need to convert all the tri-state buffers to OR-
GATE manually.

Thanks for the information

Best Regards,
Haiwen
 
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