interleaved A/D...

[RichD]

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

--
Rich

 

[Gerhard Hoffmann]

Am 18.03.23 um 23:18 schrieb RichD:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Keysight has a 100 GHz BW scope with interleaved
samplers IIRC.

Gerhard

 

[Lasse Langwadt Christensen]

søndag den 19. marts 2023 kl. 00.04.19 UTC+1 skrev Gerhard Hoffmann:

Am 18.03.23 um 23:18 schrieb RichD:
I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.
Keysight has a 100 GHz BW scope with interleaved
samplers IIRC.

Keysight UXR-Series, MSRP \"only\" $1.3mill

https://youtu.be/DXYje2B04xE

 

[Ricky]

On Saturday, March 18, 2023 at 6:18:44 PM UTC-4, RichD wrote:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

I don\'t know what the actual limits are, but the two issues are jitter on the clock, and the sampling window. We like to think in absolutes, but even the fastest sample and hold has a timing window.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Jan Panteltje]

On a sunny day (Sat, 18 Mar 2023 15:18:40 -0700 (PDT)) it happened RichD
<r_delaney2001@yahoo.com> wrote in
<f0e0baa7-174e-43f9-b1f8-28404249abc2n@googlegroups.com>:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Fasted ones I know about have a bunch of comparators
the so called flash ADCs:
analog.com/en/technical-articles/understanding-flash-adcs.html

Used for video, have one somewhere.

 

[server]

On Sat, 18 Mar 2023 15:18:40 -0700 (PDT), RichD
<r_delaney2001@yahoo.com> wrote:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Since A/D converters are not identical, they might produce slightly
different digital values even from a steady analog voltage. Thus you
might get at least 1 LSB high square wave from a constant input. Thus
adding sufficient dither is critical.

 

[Jasen Betts]

On 2023-03-18, RichD <r_delaney2001@yahoo.com> wrote:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

I suspect so, also that\'s what the fastest oscilloscopes do.

I remeber seeing traces branching and fanning out to 64 or
some other crazy number of ADCs

--
Jasen.
🇺🇦 Слава Україні

 

[John Larkin]

On Sun, 19 Mar 2023 07:06:25 GMT, Jan Panteltje <alien@comet.invalid>
wrote:

On a sunny day (Sat, 18 Mar 2023 15:18:40 -0700 (PDT)) it happened RichD
r_delaney2001@yahoo.com> wrote in
f0e0baa7-174e-43f9-b1f8-28404249abc2n@googlegroups.com>:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Fasted ones I know about have a bunch of comparators
the so called flash ADCs:
analog.com/en/technical-articles/understanding-flash-adcs.html

Used for video, have one somewhere.

I don\'t think flash is popular any more. Pipeline residual takes less
parts and less power.

I knew a guy who did a flash brute force, with 64 comparators. 6 bits
at 50 MHz. It was called the SAD-650 CAMAC module.

 

[Jan Panteltje]

On a sunny day (Sun, 19 Mar 2023 09:04:48 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<7gce1ih7gj8moksbunofti9uasa7a46bu4@4ax.com>:

On Sun, 19 Mar 2023 07:06:25 GMT, Jan Panteltje <alien@comet.invalid
wrote:

On a sunny day (Sat, 18 Mar 2023 15:18:40 -0700 (PDT)) it happened RichD
r_delaney2001@yahoo.com> wrote in
f0e0baa7-174e-43f9-b1f8-28404249abc2n@googlegroups.com>:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Fasted ones I know about have a bunch of comparators
the so called flash ADCs:
analog.com/en/technical-articles/understanding-flash-adcs.html

Used for video, have one somewhere.

I don\'t think flash is popular any more. Pipeline residual takes less
parts and less power.

I knew a guy who did a flash brute force, with 64 comparators. 6 bits
at 50 MHz. It was called the SAD-650 CAMAC module.

Sure, but did you read the link as pdf?
See page 8

8 bits is enough for most things (you can always bias).
Else use this to design a faster one (not!):

SAY GOODBYE TO CODING: MICROSOFT LAUNCHES POWER PLATFORM COPILOT
https://www.gizchina.com/2023/03/18/say-goodbye-to-coding-microsoft-launches-power-platform-copilot/

was on google news today....

I expected it to go that way, bit more and all we need is dummies doing wishes to the AI fairy.
\'Be careful what you wish for\' comes to mind too.

No more schooling needed?
We end up as a brain in a petry dish?
Are we redundant?

Job intervoew (providing any jobs are left and not already taken by AI bots):
Are you a coder?
\"Yes, see: \'AI design and build me a <your project>\'\"

AI:
\"OK, ready in 10 minutes, please enter 10 dollars...\"

 

[Phil Hobbs]

On 2023-03-19 12:04, John Larkin wrote:

On Sun, 19 Mar 2023 07:06:25 GMT, Jan Panteltje <alien@comet.invalid
wrote:

On a sunny day (Sat, 18 Mar 2023 15:18:40 -0700 (PDT)) it happened RichD
r_delaney2001@yahoo.com> wrote in
f0e0baa7-174e-43f9-b1f8-28404249abc2n@googlegroups.com>:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Fasted ones I know about have a bunch of comparators
the so called flash ADCs:
analog.com/en/technical-articles/understanding-flash-adcs.html

Used for video, have one somewhere.

I don\'t think flash is popular any more. Pipeline residual takes less
parts and less power.

I knew a guy who did a flash brute force, with 64 comparators. 6 bits
at 50 MHz. It was called the SAD-650 CAMAC module.

Yeah, flash converters sounded great, but because of the spread in the
response times (caused partly by the resistor string connected to the
other inputs of the comparators), their aperture jitter wasn\'t too good.

The first and last one I used was a TRW TDC1038, circa 1994. (I picked
it mostly for fun--I didn\'t need anything that fast, but the extra cost
didn\'t matter in a POC proto.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Dimiter_Popoff]

On 3/19/2023 11:18, upsidedown@downunder.com wrote:

On Sat, 18 Mar 2023 15:18:40 -0700 (PDT), RichD
r_delaney2001@yahoo.com> wrote:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Since A/D converters are not identical, they might produce slightly
different digital values even from a steady analog voltage. Thus you
might get at least 1 LSB high square wave from a constant input. Thus
adding sufficient dither is critical.

This is solvable by calibration, at the expense of a minor part
of the full scale (say twice the worst case error you
want to correct). I did something similar to get integral nonlinearity
from 2-3% down to below an LSB for a 13 bit convertor ...nearly
30 years ago...(can\'t be true that time passed, can it).

The real issue is the one Rick talked about, sampling window/accuracy
and of course clock jitter. And budget... .

 

[Gerhard Hoffmann]

Am 19.03.23 um 20:16 schrieb Phil Hobbs:

On 2023-03-19 12:04, John Larkin wrote:
On Sun, 19 Mar 2023 07:06:25 GMT, Jan Panteltje <alien@comet.invalid

Fasted ones I know about have a bunch of comparators
the so called flash ADCs:
analog.com/en/technical-articles/understanding-flash-adcs.html

Used for video, have one somewhere.

I don\'t think flash is popular any more. Pipeline residual takes less
parts and less power.

I knew a guy who did a flash brute force, with 64 comparators. 6 bits
at 50 MHz. It was called the SAD-650 CAMAC module.

Yeah, flash converters sounded great, but because of the spread in the
response times (caused partly by the resistor string connected to the
other inputs of the comparators), their aperture jitter wasn\'t too good.

The first and last one I used was a TRW TDC1038, circa 1994.  (I picked
it mostly for fun--I didn\'t need anything that fast, but the extra cost
didn\'t matter in a POC proto.)

We also used a 20 MSPS 8 bit Flash ADC made by TRW to digitize
and average ultrasonic signals @ 6 MHz for measuring the inner
hull in nuclear power plants. Scopes were analog then and could
not average.

Since we were one of the first customers, we were given an extra
ADC in a plastic cube. You could see the resistor ladder to the
comparators with the nekkid eye. The chip was the size of a
thumbnail.

<
https://www.flickr.com/photos/137684711@N07/52758369518/in/dateposted-public/lightbox/
>

It was the nearly 68000-sized black chip with the white TRW-Logo
in the right bottom.

I also did the top board that replaced the entire 19\" crate
in the blurred part some years later, from concept to FPGAs,
layout, soldering and software driver, and @ 200 MSPS.
The computation loop pipeline was 23 stages deep.
The Siemens ECL to 8 lanes parallel CMOS chips were just like made for
us.

> Cheers
Gerhard

 

[Fred Bloggs]

On Sunday, March 19, 2023 at 6:00:44 AM UTC-4, Jasen Betts wrote:

On 2023-03-18, RichD <r_dela...@yahoo.com> wrote:
I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.
I suspect so, also that\'s what the fastest oscilloscopes do.

I remeber seeing traces branching and fanning out to 64 or
some other crazy number of ADCs

It was probably this:

https://www.analog.com/en/analog-dialogue/articles/interleaving-adcs.html

--
Jasen.
🇺🇦 Слава Україні

 

[Fred Bloggs]

On Sunday, March 19, 2023 at 3:16:49 PM UTC-4, Phil Hobbs wrote:

On 2023-03-19 12:04, John Larkin wrote:
On Sun, 19 Mar 2023 07:06:25 GMT, Jan Panteltje <al...@comet.invalid
wrote:

On a sunny day (Sat, 18 Mar 2023 15:18:40 -0700 (PDT)) it happened RichD
r_dela...@yahoo.com> wrote in
f0e0baa7-174e-43f9...@googlegroups.com>:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Fasted ones I know about have a bunch of comparators
the so called flash ADCs:
analog.com/en/technical-articles/understanding-flash-adcs.html

Used for video, have one somewhere.

I don\'t think flash is popular any more. Pipeline residual takes less
parts and less power.

I knew a guy who did a flash brute force, with 64 comparators. 6 bits
at 50 MHz. It was called the SAD-650 CAMAC module.



Yeah, flash converters sounded great, but because of the spread in the
response times (caused partly by the resistor string connected to the
other inputs of the comparators), their aperture jitter wasn\'t too good.

The first and last one I used was a TRW TDC1038, circa 1994. (I picked
it mostly for fun--I didn\'t need anything that fast, but the extra cost
didn\'t matter in a POC proto.)

Subranging got around those kluge architectures.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

On 2023-03-20 17:12, Fred Bloggs wrote:

On Sunday, March 19, 2023 at 3:16:49 PM UTC-4, Phil Hobbs wrote:
On 2023-03-19 12:04, John Larkin wrote:
On Sun, 19 Mar 2023 07:06:25 GMT, Jan Panteltje <al...@comet.invalid
wrote:

On a sunny day (Sat, 18 Mar 2023 15:18:40 -0700 (PDT)) it happened RichD
r_dela...@yahoo.com> wrote in
f0e0baa7-174e-43f9...@googlegroups.com>:

I had a conversation of A/D converters recently, we
speculated on the fastest topology, it must be
interleaved sampling.

In principle, one could interleave without limit;
go to higher and higher time resolutions, attain
proportionately higher sampling rates. What\'s the
limit, in practice, given an unlimited budget?

We must assume a quantization, let\'s say 6 bits,
but you might suggest another.

Fasted ones I know about have a bunch of comparators
the so called flash ADCs:
analog.com/en/technical-articles/understanding-flash-adcs.html

Used for video, have one somewhere.

I don\'t think flash is popular any more. Pipeline residual takes less
parts and less power.

I knew a guy who did a flash brute force, with 64 comparators. 6 bits
at 50 MHz. It was called the SAD-650 CAMAC module.



Yeah, flash converters sounded great, but because of the spread in the
response times (caused partly by the resistor string connected to the
other inputs of the comparators), their aperture jitter wasn\'t too good.

The first and last one I used was a TRW TDC1038, circa 1994. (I picked
it mostly for fun--I didn\'t need anything that fast, but the extra cost
didn\'t matter in a POC proto.)

Subranging got around those kluge architectures.

Go on.

Cheers

Phil Hobbs