interfacing vhdl to a verilog file

[ashwin]

Hello everyone
I instantiated a vhdl file in a verilog file. It doesnt give me any
errors But i am not able to simulate a vhdl - verilog file since i dont
have a license for that . I am using Active HDL
But is this correct way of doing to get correct results. Here is a
simple example.


vhdl code

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and1 is
port(
a: in std_logic_vector(7 downto 0);
c: in std_logic_vector(7 downto 0);
b: out std_logic_vector(7 downto 0)
);
end and1;

--}} End of automatically maintained section

architecture and1 of and1 is
begin
b<=a and c;
-- enter your statements here --

end and1;


-----------------------------verilog main
module----------------------------------


`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
// and may be overwritten
//{module {main_And}}
module main_And (input1,input2,output1);
input [7:0] input1;
input [7:0] input2;
output [7:0] output1;

and1 U0( //instantiation
of vhdl file done here.
..a(input1),.c(input2),.b(output1));
endmodule