Interfacing DS92LV1021 with FPGA serdes

J

j.

Guest
Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
Serializer) to send data. Unfortunately it also sends start and stop
bits, 12-bit each word total (@480MHz). Task is to build a receiver in
FPGA. However, both Xilinx and Altera built-in SERDES circuits support
only 10-bit words ("deserialization factor"). Is there any way to
interface them with the above DS92LV1021 chip?
 
On Dec 9, 11:02 am, "j." <garas....@gmail.com> wrote:
Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
Serializer) to send data. Unfortunately it also sends start and stop
bits, 12-bit each word total (@480MHz). Task is to build a receiver in
FPGA. However, both Xilinx and Altera built-in SERDES circuits support
only 10-bit words ("deserialization factor"). Is there any way to
interface them with the above DS92LV1021 chip?
Click to expand...
Many of the newer Xilinx chips can do deserialization at these rates
using standard
I/O's rather than the "GTP" or "Rocket I/O". I expect newer Altera
parts can do the
same. For Xilinx there are some app notes on "high-speed LVDS" you
can look for
on their site.

-- Gabor
 
On 12/9/2010 11:50 AM, Gabor wrote:
On Dec 9, 11:02 am, "j."<garas....@gmail.com> wrote:
Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
Serializer) to send data. Unfortunately it also sends start and stop
bits, 12-bit each word total (@480MHz). Task is to build a receiver in
FPGA. However, both Xilinx and Altera built-in SERDES circuits support
only 10-bit words ("deserialization factor"). Is there any way to
interface them with the above DS92LV1021 chip?

Many of the newer Xilinx chips can do deserialization at these rates
using standard
I/O's rather than the "GTP" or "Rocket I/O". I expect newer Altera
parts can do the
same. For Xilinx there are some app notes on "high-speed LVDS" you
can look for
on their site.

-- Gabor
Click to expand...
Be careful here, this chip embeds the clock in the data stream. In
other words, it does not send a separate synchronous clock along with
the serialized data.

You will be forced into an FPGA that has something like a DPA (dynamic
phase aligner) to find the eye of the data and extract a clock.
Typically it is the higher end family of FPGA's that offer these types
of interfaces, but they come with a high price tag.

It might just be more cost effective to use the receiver chip by
National and go into your FPGA with parallel data. You could then
easily get into a very cost effective FPGA.

Rob
 
On 9 Dez., 17:02, "j." <garas....@gmail.com> wrote:
Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
Serializer) to send data. Unfortunately it also sends start and stop
bits, 12-bit each word total (@480MHz). Task is to build a receiver in
FPGA. However, both Xilinx and Altera built-in SERDES circuits support
only 10-bit words ("deserialization factor"). Is there any way to
interface them with the above DS92LV1021 chip?
Click to expand...
The 12 bit word length is a non issue: use a 6x deserializer. You get
your 12 bit word as two 6 bit nibbles. Piece of cake.
However, the clock recovery that the other poster talks about is more
difficult.
Without a PLL or other specialized support circuitry you would need 3x
oversampling to recover the clock and phase reliably in a digital
circuit.
Therefore you end up at 1440Mbps, which is just out of reach for a
virtex-5 (710MHz fmax = 1420Mbps).
With 103% VCC you should be OK on a virtex-5.

Kolja
 
"j." <garas.rez@gmail.com> writes:

Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
Serializer) to send data. Unfortunately it also sends start and stop
bits, 12-bit each word total (@480MHz). Task is to build a receiver in
FPGA. However, both Xilinx and Altera built-in SERDES circuits support
only 10-bit words ("deserialization factor"). Is there any way to
interface them with the above DS92LV1021 chip?
Click to expand...
I have done this for a very similar link (just in LUTs) in a Spartan3E
at 27MHz, IIRC it would probably go to 30ish MHz - pushing it to 40MHz
would be beyond it.

I also had the benefit of enough control of the system to get it to
send a series of all-zeros words at startup which made finding the
sampling point much easier!

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
 
Thank you for the answers.

Be careful here, this chip embeds the clock in the data stream.  In
other words, it does not send a separate synchronous clock along with
the serialized data.
Click to expand...
Actually, AFAIK this "embedded clock" is indeed derived from the
start-stop bit. To get synchronized the transmitter needs to issue
some kind of synchronization pattern, I can imagine simply "all
ones".
In this case the stop bit is the only zero in the data stream, can be
used to start synchronization.


You will be forced into an FPGA that has something like a DPA (dynamic
phase aligner) to find the eye of the data and extract a clock.
Typically it is the higher end family of FPGA's that offer these types
of interfaces, but they come with a high price tag.
Click to expand...
In my case the situation is a bit easier, both the transmitter and
the receiver uses the same clock source, thus the frequency
is always the same, the phase might be different (even for
the data channels, as the wires have slightly different length)
but constant. Thus if the correct phase has been established
it remains correct.

Of course in presence of a considerable jitter the phase needs
to get realigned in some way.


It might just be more cost effective to use the receiver chip by
National and go into your FPGA with parallel data.  You could then
easily get into a very cost effective FPGA.
Click to expand...
The problem is that the FPGA should receive data from 96 similar
10:1 LVDS Channels. There is no board space for 96 National chips.

In addition no FPGA has 96 independent embedded PLLs.

Janos
 
On 10 Dez., 09:52, Kolja Sulimma <ksuli...@googlemail.com> wrote:
On 9 Dez., 17:02, "j." <garas....@gmail.com> wrote:

Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
Serializer) to send data. Unfortunately it also sends start and stop
bits, 12-bit each word total (@480MHz). Task is to build a receiver in
FPGA. However, both Xilinx and Altera built-in SERDES circuits support
only 10-bit words ("deserialization factor"). Is there any way to
interface them with the above DS92LV1021 chip?

The 12 bit word length is a non issue: use a 6x deserializer. You get
your 12 bit word as two 6 bit nibbles. Piece of cake.
However, the clock recovery that the other poster talks about is more
difficult.
Without a PLL or other specialized support circuitry you would need 3x
oversampling to recover the clock and phase reliably in a digital
circuit.
Therefore you end up at 1440Mbps, which is just out of reach for a
virtex-5 (710MHz fmax = 1420Mbps).
With 103% VCC you should be OK on a virtex-5.

Kolja
Click to expand...
We are successfully deserializing a 60MWord/s (720Mbps) data-stream
with a Cyclone III by using DPA. However, it is tricky and we do also
not achieve the same cable-length as with the National deserializer
(but reasonable lengths). So if there is no real requirement (cost,
space) to get rid of the external deserializer, it will be the easier
option to use the dedicated chip.

Thomas

www.entner-electronics.com
 
On 10 Dez., 11:50, "j." <garas....@gmail.com> wrote:

In my case the situation is a bit easier, both the transmitter and
the receiver uses the same clock source, thus the frequency
is always the same, the phase might be different (even for
the data channels, as the wires have slightly different length)
but constant. Thus if the correct phase has been established
it remains correct.
Click to expand...
This should make things much easier, especially if you have the same
routing-delay on all channels. It would be difficult if you have to
sample the channels all on a different phase (maybe you could adjust
the phase on the transmitter side).

Thomas

www.entner-electronics.com
 
On 10 Dez., 12:08, Thomas Entner <thomas.entne...@gmail.com> wrote:
On 10 Dez., 11:50, "j." <garas....@gmail.com> wrote:

In my case the situation is a bit easier, both the transmitter and
the receiver uses the same clock source, thus the frequency
is always the same, the phase might be different (even for
the data channels, as the wires have slightly different length)
but constant. Thus if the correct phase has been established
it remains correct.

This should make things much easier, especially if you have the same
routing-delay on all channels. It would be difficult if you have to
sample the channels all on a different phase (maybe you could adjust
the phase on the transmitter side).
Click to expand...
If the FPGA has access to the clock source of the serializer, only the
phase has
to be determined at the receiver. That is actually pretty easy if you
can set the transmitter
to a know training pattern.
If you have a CPU in your system you can write software that controls
the variable
phase shift of an IDELAY to search for the right phase. This can be
done one input
at a time. Once you know the correct delay setting for your 96 inputs
your are good to go.

At 480Mbps there is not much to worry about. We do that at 1250Mbps
and have a reliable
sampling window of quite a few delay taps.


Kolja
cronologic.de
 
Kolja Sulimma <ksulimma@googlemail.com> writes:

If the FPGA has access to the clock source of the serializer, only the
phase has
to be determined at the receiver. That is actually pretty easy if you
can set the transmitter
to a know training pattern.
If you have a CPU in your system you can write software that controls
the variable
phase shift of an IDELAY to search for the right phase. This can be
done one input
at a time. Once you know the correct delay setting for your 96 inputs
your are good to go.
Click to expand...
Or if no CPU, then a small state machine can also do the job (either
sweeping an IDELAY, or in my case the variable phase-shift of a DCM).

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
 
j. wrote:
Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
Serializer) to send data. Unfortunately it also sends start and stop
bits, 12-bit each word total (@480MHz). Task is to build a receiver in
FPGA. However, both Xilinx and Altera built-in SERDES circuits support
only 10-bit words ("deserialization factor"). Is there any way to
interface them with the above DS92LV1021 chip?
Click to expand...
Have a look at:
http://www.missinglinkelectronics.com/files/papers/MLE-TB20091127.pdf

Looks like that one matches ;-)

Regards,
Lorenz
 
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