Interfacing DDR RAMs to Xilinx Virtex 2 Pro on Digilent boar

Hello,

I am graduate student in the Dept. of Computer Sc. & Engg. in
USF.
We are using a Digilent XUP2vpPro board for one of our research
projects. I am trying to interface a Kingston 512 MB DDR RAM in DIMM
to Xilinx virtex 2 Pro FPGA. The DDR RAM is the same that is
recommended at the board's webpage. I am using the MIG 007 tool to
generate the memory controller and modify it according to our needs.

I was looking for some specifications of the DDR RAM like number
of
banks, # of row and column address counts. I was curious if there are
any specification docs that lists these details from Kingston?

Also since the DDR Memory is from a third party, xilinx does not
provide any simulation libraries (like it does for BRAM's for eg).
Hence the only way to do a system level simulation is either testing
"on-board" or using ChipScope Pro. I was curious if RTL level models
or simulation libraries are provided for these DDR RAMs so that I
could do a system simulation from inside ISE itself?

If there aee reference designs for the memory controllers for
DDR
RAMs for interfacing to Xilinx V2P, that would be greatly helpful as
well.

Any sort of tips/suggestions will be helpful.

Thanks,
Koustav

 

[kunal]

On May 15, 3:30 pm, kousta...@gmail.com wrote:

Hello,

I am graduate student in the Dept. of Computer Sc. & Engg. in
USF.
We are using a Digilent XUP2vpPro board for one of our research
projects. I am trying to interface a Kingston 512 MB DDR RAM in DIMM
to Xilinx virtex 2 Pro FPGA. The DDR RAM is the same that is
recommended at the board's webpage. I am using the MIG 007 tool to
generate the memory controller and modify it according to our needs.

I was looking for some specifications of the DDR RAM like number
of
banks, # of row and column address counts. I was curious if there are
any specification docs that lists these details from Kingston?

Also since the DDR Memory is from a third party, xilinx does not
provide any simulation libraries (like it does for BRAM's for eg).
Hence the only way to do a system level simulation is either testing
"on-board" or using ChipScope Pro. I was curious if RTL level models
or simulation libraries are provided for these DDR RAMs so that I
could do a system simulation from inside ISE itself?

If there aee reference designs for the memory controllers for
DDR
RAMs for interfacing to Xilinx V2P, that would be greatly helpful as
well.

Any sort of tips/suggestions will be helpful.

Thanks,
Koustav

now xilinx come up with synthesizable vhdl/verilog code for ddr/
ddr2...The MIG tool (only for window verion) give wide flavour to
interface ddr/ddr2..
enjoy
fpga consultant
dichign solution
www.dichign.com