interface declaration with instance & modport in generate

[vincent]

Hi everyone,
I want to make optional port on an interface controlled by a parameter ie

interface foo #(F=0)
generate if (F>0) begin
logic foo;
modport sl(input foo);
end
...
endinterface

Is this legal systemverilog? From the spec it seems it is but NCSim doesn't seem to like it. Also it's not clear (to me) from the spec whether one can define modports in incremental fashion, ie
...
modport slv(input a);
modport slv(input b); etc.

is this possible or should one put all into a single modport?

thanks.

 

[unfrostedpoptart]

On Friday, May 17, 2013 11:16:03 PM UTC-7, vincent wrote:

Hi everyone,

I want to make optional port on an interface controlled by a parameter ie

interface foo #(F=0)
generate if (F>0) begin
logic foo;
modport sl(input foo);
end ...

endinterface

Is this legal systemverilog? From the spec it seems it is but NCSim doesn't seem to like it.

Not positive since my project for the last couple of years isn't using SVIs, but from my previous project, I don't remember anything like this. Instead, you define the different modports and then, using generate in the instantiating module, choose which mod port to use for the SVI.

As for NCSim, Cadence is way behind in supporting all the parts of SV, and that's not even taking into account new stuff from the recent IEEE spec.

Also it's not clear (to me) from the spec whether one can define modports in incremental fashion, ie

modport slv(input a);
modport slv(input b); etc.
is this possible or should one put all into a single modport?

I'm 99.9% sure you can't do this. Again, define different mod port for the entire interface for difference cases and then select which one in the instantiation.

 

On Sunday, May 19, 2013 4:51:16 PM UTC-7, unfrostedpoptart wrote:

On Friday, May 17, 2013 11:16:03 PM UTC-7, vincent wrote:

Hi everyone,



I want to make optional port on an interface controlled by a parameter ie



interface foo #(F=0)

generate if (F>0) begin

logic foo;

modport sl(input foo);

end ...



endinterface



Is this legal systemverilog? From the spec it seems it is but NCSim doesn't seem to like it.



Not positive since my project for the last couple of years isn't using SVIs, but from my previous project, I don't remember anything like this. Instead, you define the different modports and then, using generate in the instantiating module, choose which mod port to use for the SVI.



As for NCSim, Cadence is way behind in supporting all the parts of SV, and that's not even taking into account new stuff from the recent IEEE spec.



Also it's not clear (to me) from the spec whether one can define modports in incremental fashion, ie



modport slv(input a);

modport slv(input b); etc.

is this possible or should one put all into a single modport?



I'm 99.9% sure you can't do this. Again, define different mod port for the entire interface for difference cases and then select which one in the instantiation.
I'm 100% sure you can't do this.

What you can do use parameterize a type that is a structure, and then change the structure to have the fields you need. You will have to use different structs for inputs and outputs if you need to declare directions.