Interface Bidir IO datalines to dualport RAM within FPGA - U

[karthik]

======
URGENT
======

I have a small query and if possible do help me on this issue.

|
|FPGA |=========
| -->| Din
Processor<->|<----> | This is my dual port memory
data line | <--| Dout
(bidir) | |=========
|
|

I have my main module dataline to be bidirectional so that there is no
separate datalinein and separate datalineout. So Iam making it to be
configured as input and output using the read enable and write enable.
as shown below… I need to know whether its correct or not.

I have no doubts with the memory code below, its working fine when I
make it a read only memory,so that in in the top level indicated below
Ive made the ebmdat as out and directly connected it to the memory out
port.So on reset I hardcode some data and when attempted to read,it
worked fine. But when Bidirectional pin is used as shown below I got
problems.

This is My Top Level accesing my Memory
---------------------------------------

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ebmem_top is
port ( ebmclk : in std_logic;
ebmnwt : in std_logic;
ebmnrd : in std_logic;
ebmadd : in std_logic_vector(5 downto 0);
ebmncs : in std_logic;
ebmdat : inout std_logic_vector(7 downto 0));
--It has only a single Port and it should Connect both
input
and output of memory according to ebmwt and ebmrd, which is
achieved with two temporary signals datain and dataout
end ebmem_top;

architecture arc of ebmem_top is
component ebmem ----- MEMORY and its defn in nxt page
------
port (ebmclk : in std_logic;
ebmnwt : in std_logic;
ebmadd : in std_logic_vector(5 downto 0);
ebmncs : in std_logic;
ebmdati : in std_logic_vector(7 downto 0);
ebmdato : out std_logic_vector(7 downto 0));
end component;

signal datain, dataout : std_logic_vector(7 downto 0);

begin

ebmemory : ebmem port map(ebmclk,ebmnwt,ebmadd,ebmncs,datain,dataout);

process(ebmclk)
begin

if(ebmclk='1' and ebmclk'event)then -- THIS IS WHERE THE SWAPPING
HAPPENS
if(ebmnwt = '0')then -- ebmnwt is active low signal
datain <= ebmdat;
ebmdat <= (others =>'Z');
else
ebmdat <= dataout;
end if;
end if;

end process;

end arc;

=================================================================

Assume that its my Memory Core
------------------------------

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ebmem is
port ( ebmclk : in std_logic;
ebmnwt : in std_logic;
ebmadd : in std_logic_vector(5 downto 0);
ebmncs : in std_logic;
ebmdati : in std_logic_vector(7 downto 0);
ebmdato : out std_logic_vector(7 downto 0));
end ebmem;

architecture ebm_arch of ebmem is

type memarray is array(63 downto 0) of std_logic_vector(7 downto 0);
signal memloc : memarray;

signal read_a : std_logic_vector(5 downto 0);

begin
process(ebmclk)
begin

if (ebmclk = '1' and ebmclk'event) then
if (ebmnwt = '0' and ebmncs = '0' ) then
memloc(conv_integer(ebmadd)) <= ebmdati;
end if;

read_a <= ebmadd;
end if;
end process;

ebmdato <= memloc(conv_integer(read_a));

end ebm_arch;
==================================================================

 

[Paulo Dutra]

I'm assuming a synthesis tool cannot work with the 'process'
block as you have it coded. Otherwise, you may find support
in comp.lang.vhdl forum.

You should describe the registered input path as one
process, the registered output path as another, and the
tristate as a continous assignment.



-- Registered Input path
process(ebmclk)
begin
if (ebmclk'event and ebmclk='1') then
datain <= ebmdat;
end if;

-- Registered Output path with tri-state
process(ebmclk)
begin
if (ebmclk'event and ebmclk='1') then
dataout_reg <= dataout;
end if;

ebmdat <= dataout_reg when enable = '1' else (others => 'Z') ;

process(ebmclk)
begin

if(ebmclk='1' and ebmclk'event)then -- THIS IS WHERE THE SWAPPING
HAPPENS
if(ebmnwt = '0')then -- ebmnwt is active low signal
datain <= ebmdat;
ebmdat <= (others =>'Z');
else
ebmdat <= dataout;
end if;
end if;

--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
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\_\/.\ San Jose, California 95124-3450 USA