R
ramnarayan
Guest
Hi,
what's the difference when write the sequences, properties in an
interface block and module.
what's the difference when write the sequences, properties in an
interface block and module.
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J
Jonathan Bromley
Guest
On 2 Nov 2006 00:32:47 -0800, "ramnarayan" <ramlh2004@gmail.com>
wrote:
Very little difference - interfaces and modules have the same
timing semantics. In practice, though, interfaces are probably
a good place to put assertions, so that you get the assertions
every time you use the interface.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
wrote:
I assume you're talking about SystemVerilog?Hi,
what's the difference when write the sequences, properties in an
interface block and module.
Very little difference - interfaces and modules have the same
timing semantics. In practice, though, interfaces are probably
a good place to put assertions, so that you get the assertions
every time you use the interface.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
A
Ajeetha
Guest
In SV, interface is intended to capture communication - meaning all to
do with how 2 (or more) blocks talk to each other inclduing:
1. Signals, directions, timing
2. Protocol checks/properties/assertions/assumptions
3. Coverage - aka compliance for a defined protocol
4. Tasks to do misc functions such as "bandwidth measuring" etc.
So assertions are ideal candidates in interface. It is little incorrect
to compare them against modules - modules are meant for actual data
processing/logc modeling, module ports can contain complete interface
(and not the other way around). Now any assumption that a RTL designer
makes, coverage that she/he believes is needed, can be captured using
assertions/coverage. So it is not either-or, rather both.
HTH
Ajeetha, CVC
www.noveldv.com
ramnarayan wrote:
do with how 2 (or more) blocks talk to each other inclduing:
1. Signals, directions, timing
2. Protocol checks/properties/assertions/assumptions
3. Coverage - aka compliance for a defined protocol
4. Tasks to do misc functions such as "bandwidth measuring" etc.
So assertions are ideal candidates in interface. It is little incorrect
to compare them against modules - modules are meant for actual data
processing/logc modeling, module ports can contain complete interface
(and not the other way around). Now any assumption that a RTL designer
makes, coverage that she/he believes is needed, can be captured using
assertions/coverage. So it is not either-or, rather both.
HTH
Ajeetha, CVC
www.noveldv.com
ramnarayan wrote:
Hi,
what's the difference when write the sequences, properties in an
interface block and module.