interconnecting two same type of components

[deep]

I am trying to design a component that could be used multiple times. For ex
C1 an c2. Now the ports of components are defined as :

component c is(
rst: in std_logic;
clk : in std_logic;
a: inout std_logic;
b: inout std_logic);

...
...
c1: c
port map(
rst=>rst,
clk=>clk,
a=> x, --a is output
b=> y); --b is input

c2: c
port map(
rst=>rst,
clk=>clk,
a=> y, --a is output
b=> x);--a is output


rst and clk are global input signals. "x" and "y" are used as wires
interconnecting modules c1 and c2. "x" works as output of c1 and input of
c2. "y" works as output of c2 and input of c1.c1 works in master mode and
c2 works in slave mode. when asynchronous reset is applied, x is mapped as
high. and then the operation starts subsequently with the logic applied.

my problem is that "x" always remains at undefined level inspite of the
fact that I forced it high when rst='1'. and same happens with "y" though
it is derived after ther is some change on "x".

I am synthesing the code in Xilinx and simulating on Modelsim.
could somebody help me out .

--deep