Guest
Hi All,
I was wondering is it possible to create a VHDL testbench interactively
using Active HDL? Similar to what is available with Xilinx ISE. If not
, are their any other methods of achieving something similar via other
means ?
Cheers Luca
I was wondering is it possible to create a VHDL testbench interactively
using Active HDL? Similar to what is available with Xilinx ISE. If not
, are their any other methods of achieving something similar via other
means ?
Cheers Luca