Integers only as generics?

[Acciduzzu]

Dear all,

I'm currently designing a peripheral device in VHDL, which is
connected to a 32-bit bus. As I want to make its position in the
memory map parametrizable, I defined a mask as a generic constant
parameter. Here is the code sample below:

entity bus_peripheral is
generic(
DEVICE_ID : std_logic_vector(7 downto 0);
REVISION_NO : std_logic_vector(7 downto 0);

BASE_ADDR : std_logic_vector(31 downto 0); -- Base address
on the bus

-- timing settings (100MHz clk)
T1 : integer := 10;
T2 : integer := 28;
T3 : integer := 23
);
port(
clk : in std_logic;
rst : in std_logic;

-- bus signals
--
);
end entity;

The above code compiles with no problems under ModelSim with "check
for synthesis" enabled, yet it makes Synopsys Design Compiler issue an
error. The error message I get is:
"Only generics of type INTEGER are supported for synthesys
(VHDL-2024)".
Is that really a limitation of Synopsys DC? If so, I am really
disappointed... I had the impression DC is the best synth tool around
. Did you guys have this problem with other tools? Is any workaround
possible?

Thanks for answers

 

[Ralf Hildebrandt]

Hi Acciduzzu

entity bus_peripheral is
generic(
DEVICE_ID : std_logic_vector(7 downto 0);
REVISION_NO : std_logic_vector(7 downto 0);

BASE_ADDR : std_logic_vector(31 downto 0); -- Base address
on the bus

-- timing settings (100MHz clk)
T1 : integer := 10;
T2 : integer := 28;
T3 : integer := 23
);

The above code compiles with no problems under ModelSim with "check
for synthesis" enabled, yet it makes Synopsys Design Compiler issue an
error. The error message I get is:
"Only generics of type INTEGER are supported for synthesys
(VHDL-2024)".

What's the problem? There are conversion functions, that help you using
integer als generic parameters.

e.g.:

DEVICE_ID : integer:=to_integer(unsigned("00000000"));


O.k., you have to convert all parameters to integer, when instanziating
a component and often you have to reconvert the generic parameters to
use them inside the component, but it's only a little bit more code to
write.


Ralf

 

[Acciduzzu]

Ralf,

converting them to integers is a good solution, but it only works for
parameters that are less than 32-bit wide! I heard, however, that the
new VHDL standard - 2004? - will allow integers with unlimited size.
Until then... waiting for some practical solutions

 

[Mike Treseler]

converting them to integers is a good solution, but it only works for
parameters that are less than 32-bit wide! I heard, however, that the
new VHDL standard - 2004? - will allow integers with unlimited size.
Until then... waiting for some practical solutions

Consider passing just the vector lengths as generic
and use that in the architecture or process to declare
the vector or natural type you really want.

-- Mike Treseler

 

[Allan Herriman]

On 22 Sep 2003 05:59:52 -0700, pmihail@gmx.net (Acciduzzu) wrote:

[snip]

The above code compiles with no problems under ModelSim with "check
for synthesis" enabled,

Modelsim's "check for synthesis" doesn't actually do many useful
checks.

yet it makes Synopsys Design Compiler issue an
error. The error message I get is:
"Only generics of type INTEGER are supported for synthesys
(VHDL-2024)".
Is that really a limitation of Synopsys DC? If so, I am really
disappointed... I had the impression DC is the best synth tool around
.

It's not a very good tool in terms of language coverage.

Did you guys have this problem with other tools? Is any workaround
possible?

Your code should work well in other synth tools, e.g. Leonardo,
Synplify.

Regards,
Allan.