Integer variable

[bir]

I have a for-loop in side my rtl to reset a RAM as below


always @(negedge reset_n or posedge tclk)
begin
if (!reset_n)
begin
for (i=0; i<8; i=i+1)
ram <= {32{1'b0}};
.......
.....

I have declared i as integer in my internal signal declaration . But I
was wondering what will be the best way of declaring i (integer or
register) from synthesis point of view.

Thanks

 

bir wrote:

But I
was wondering what will be the best way of declaring i (integer or
register) from synthesis point of view.

I doubt that the synthesis tool cares.

But for a human reader, using an integer makes it
clearer that this is an abstract variable used to
specify the algorithm, not something intended to
represent a hardware register.

 

[Andy]

On Jan 30, 10:35 am, "bir" <ritwikbis...@gmail.com> wrote:

I have a for-loop in side my rtl to reset a RAM as below

always @(negedge reset_n or posedge tclk)
begin
if (!reset_n)
begin
for (i=0; i<8; i=i+1)
ram <= {32{1'b0}};
.......
.....

I have declared i as integer in my internal signal declaration . But I
was wondering what will be the best way of declaring i (integer or
register) from synthesis point of view.

Thanks

HDL loops are unrolled for synthesis, therefore the loop index becomes
effectively (from a synthesis point of view) static, so it does not
matter from a synthesis point of view. Integers probably simulate
faster (especially in vhdl, not sure about verilog).

Andy