Integer to slv

[stephen henry]

Hi all,

I'm having difficulty figuring out how to fix an integer to
std_logic_vector function that I threw together:

function integer_to_slv (
invect, bits : integer)
return std_logic_vector is


variable n : std_logic_vector(bits-1 downto 0) := (others => '0');
variable temp : integer := invect;
begin

for i in n'reverse_range loop
if temp mod 2 = 1 then
n(i) := '1';
end if;
temp := temp / 2;
end loop;

return n;

end function integer_to_slv;

The function works okay; however, when it comes to converting negative
integers to std_logic_vector, the sign bit is lost (the result always
being positive). It seems that in the final iteration of the loop, the
temp variable corresponds to 0000....0000(sign bit), this however
doesn't work with the mod function so the result is always negative.
How could I fix this?

Thanks for any help

Steve

 

[Parikshit Kumar]

any particular reason you don't want to use already available functions in
numeric_std package

std_logic_vector(to_signed(invect, bits) )

"stephen henry" <stehenry@yahoo.com> wrote in message
news:845db307.0309101457.5d198b1f@posting.google.com...

Hi all,

I'm having difficulty figuring out how to fix an integer to
std_logic_vector function that I threw together:

function integer_to_slv (
invect, bits : integer)
return std_logic_vector is


variable n : std_logic_vector(bits-1 downto 0) := (others => '0');
variable temp : integer := invect;
begin

for i in n'reverse_range loop
if temp mod 2 = 1 then
n(i) := '1';
end if;
temp := temp / 2;
end loop;

return n;

end function integer_to_slv;

The function works okay; however, when it comes to converting negative
integers to std_logic_vector, the sign bit is lost (the result always
being positive). It seems that in the final iteration of the loop, the
temp variable corresponds to 0000....0000(sign bit), this however
doesn't work with the mod function so the result is always negative.
How could I fix this?

Thanks for any help

Steve

 

[stephen henry]

"Parikshit Kumar" <reply to group> wrote in message news:<3f603dd6$0$251$4d4ebb8e@read-nat.news.nl.uu.net>...

any particular reason you don't want to use already available functions in
numeric_std package

std_logic_vector(to_signed(invect, bits) )

Yes, I'm aware that function that do this already exist. The reason I
am not using them is to further my knowledge of VHDL, hence the reason
I not having too much success getting it to work!

 

[Ralf Hildebrandt]

stephen henry wrote:

I'm having difficulty figuring out how to fix an integer to
std_logic_vector function that I threw together:

Why don't you use the build-in-functions?

Library IEEE;
use IEEE.numeric.std.all;


some_slv<=std_logic_vector( to_unsigned(some_integer,bitwidth) );



Ralf

 

[Mike Treseler]

stephen henry wrote:

Yes, I'm aware that function that do this already exist. The reason I
am not using them is to further my knowledge of VHDL, hence the reason
I not having too much success getting it to work!

Have a look at the numeric_std source that comes with your simulator.

-- Mike Treseler