Integer to SLV type conversion?

[Brandon]

I previously had the following conversion:

fxdbin_v(j) := to_X01(bit'val(int_v mod 2));

but I had to remove this since it would not synthesize bit'val in XST.

So....

<SNIP>
function ...
...
variable int_v : integer range -2**(m+n) to 2**(m+n)-1;
variable fxdbin_v : std_logic_vector(m+n downto 0);
...

begin
...
fxdbin_v(j) := std_logic_vector( to_unsigned( (int_v mod 2),1 ) );
...
</SNIP>

The compiler is giving the error:
** Error: C:/Modeltech_6.0c/user/user_utils.vhd(122): Assignment target
type std_ulogic is different from expression type std_logic_vector.

I realize that fxdbin_v is an array of std_logic, soI also tried:
fxdbin_v(j) := std_logic( to_unsigned( (int_v mod 2),1 ) );
and every other combination I could think of. Silly type conversions!

Thanks,
-Brandon

 

[ajahn]

Hi Brandon,
if you do a std_logic_vector( to_unsigned( something, 1)) the
result will be a std_logic_vector(0 downto 0). So, if you want to
assign that to fxdbin_v(j) -j is an integer type i guess- you have to
specify which std_logic value from the array you want. Since there is
only one, this is easy ;-) Try:
fxdbin_v(j) := std_logic_vector( to_unsigned( (int_v mod 2),1 ) )(0);
Or do this:
fxdbin_v(j downto j) := std_logic_vector( to_unsigned( (int_v mod 2),1
) );

I hope, that helps ...
Cheers,
Andreas

 

[sionpark]

Hi Brandon,
I think you'll find an answer at
http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html
I hope, that helps..