integer synthesis

[bir]

Hi

How does Synopsys synthesis tool treat integar data type.

integer i;

always @(negedge ntrst or posedge clk)
begin
if (!ntrst)
begin
for (i=0 ; i< BUFFER_WIDTH ; i=i+1)
buffer <= 32'd0;
...................
...................

In my design I am getting some extra flops and I have no idea where
they are located as synopsys doesn't explicitly say anything about it,
only it shows in my "Total Flip Flop Count".



Thanks
Bir

 

[Ralf Hildebrandt]

bir schrieb:

How does Synopsys synthesis tool treat integar data type.

integer i;

always @(negedge ntrst or posedge clk)
begin
if (!ntrst)
begin
for (i=0 ; i< BUFFER_WIDTH ; i=i+1)
buffer <= 32'd0;
...................
...................

If BUFFER_WIDTH is a parameter (fixed), then i will synthesize to
nothing you can see. The synthesis tool makes a static evaluation of the
for-loop, unrolls it and maps the body of the loop to the desired
circuit elements.


To give you a totally different example:

always @(nededge reset OR posedge clk)
begin
if (reset==1'b0) begin
i<=0;
end else /*if posedge clk*/ begin
i<=i+1;
end //if
end //always

In this example i will synthesize to flipflops (plus incrementer logic).
The synthesis result of type integer is not fixed to a special circuit
element. It depends on what you model.

Ralf

 

[Utku Özcan]

Hi Ralf,

I think this guy wants to initialize its memory to a known value, like
0. Initialization of RAMs is a simulation setup issue, and thus they
can be initialized using Verilog standard PLI tasks $readmemb/h.

I would have done:

----
always @(negedge ntrst or posedge clk)
begin
if (!ntrst)
begin
$readmemb ("buffer.dat", buffer);
end
else
....
----

Utku.

On 12 Mrz., 20:48, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:

bir schrieb:

How does Synopsys synthesis tool treat integar data type.

integer i;

always @(negedge ntrst or posedge clk)
begin
if (!ntrst)
begin
for (i=0 ; i< BUFFER_WIDTH ; i=i+1)
buffer <= 32'd0;
...................
...................

If BUFFER_WIDTH is a parameter (fixed), then i will synthesize to
nothing you can see. The synthesis tool makes a static evaluation of the
for-loop, unrolls it and maps the body of the loop to the desired
circuit elements.

To give you a totally different example:

always @(nededge reset OR posedge clk)
begin
if (reset==1'b0) begin
i<=0;
end else /*if posedge clk*/ begin
i<=i+1;
end //if
end //always

In this example i will synthesize to flipflops (plus incrementer logic).
The synthesis result of type integer is not fixed to a special circuit
element. It depends on what you model.

Ralf