instantiation to reused module

Hello,
I want to use some module in my design several times. Each module will
have its own parameters for address and data width.
I have generated two different memory modules with coregen, and I’m
having trouble to instantiate the different memory to each reused
module.
Is it possible to do it in Verilog?

Thank you,
J

 

[Jason Zheng]

On Mon, 16 Jun 2008 08:00:32 -0700 (PDT)
japonetz@gmail.com wrote:

Hello,
I want to use some module in my design several times. Each module will
have its own parameters for address and data width.
I have generated two different memory modules with coregen, and I’m
having trouble to instantiate the different memory to each reused
module.
Is it possible to do it in Verilog?

Thank you,
J

I don't see how that's a problem, unless they have the same module
names.

--
"Humor is a drug which it's the fashion to abuse."
-- William Gilbert

 

[Jonathan Bromley]

On Tue, 17 Jun 2008 00:22:26 -0700 (PDT), japonetz@gmail.com wrote:

At the top module I want to use the same module twice, but each module
will have different parameters set:

test_module #(ADDSIZE_A, DATASIZE_A) A (...);
test_module #(ADDSIZE_B, DATASIZE_B) B (...);

Inside the module A I want to instantiate module RAM_32X32.
Inside the module B I want to instantiate module RAM _32X128.

Conditional generate is your friend.

module test_module #(parameter ASIZE=1, DSIZE=1) (...ports...);

... usual module-level stuff: signals, etc ...

generate
case (DSIZE)
32:
RAM_32X32 ram(...);
128:
RAM_32X128 ram(...);
default:
initial
$display("BAD PARAM %m #(.DSIZE=%0d), \
DSIZE must be 32 or 128", DSIZE);
endcase
endgenerate

endmodule

Strictly speaking the generate/endgenerate keywords are optional,
but I like to use them because it clarifies what I'm doing with
the special kind of "case" statement.
NOTE that it is NOT inside an initial or always block, but
appears at the top level of the module. The error-trap
is not brilliant, but at least it will give you some
useful information if you set a parameter value for which
you haven't chosen a suitable module.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

Hello,
I’ll try to explain it in a little more details:

At the top module I want to use the same module twice, but each module
will have different parameters set:

test_module #
( ADDSIZE_A,
DATASIZE_A
)
A
(
.inputs(inputsA),
.outputs(outputsA)
);

test_module #
( ADDSIZE_B,
DATASIZE_B
)
B
(
.inputs(inputsB),
.outputs(outputsB)
);


Inside the module A I want to instantiate module RAM_32X32.

Inside the module B I want to instantiate module RAM _32X128.

RAM_32X32 and RAM _32X128 are different Verilog files, generated by
megacore.

What is the right way to do it (if any)?

Regards,
J


On Jun 16, 7:43 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:

On Mon, 16 Jun 2008 08:00:32 -0700 (PDT)

japon...@gmail.com wrote:
Hello,
I want to use some module in my design several times. Each module will
have its own parameters for address and data width.
I have generated two different memory modules with coregen, and I’m
having trouble to instantiate the different memory to each reused
module.
Is it possible to do it in Verilog?

Thank you,
J

I don't see how that's a problem, unless they have the same module
names.

--
"Humor is a drug which it's the fashion to abuse."
                -- William Gilbert

 

Hello Jonathan,
That's exactly what I've been looking for!
Thanks a lot!

Regards,
J

On Jun 17, 11:02 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Tue, 17 Jun 2008 00:22:26 -0700 (PDT), japon...@gmail.com wrote:
At the top module I want to use the same module twice, but each module
will have different parameters set:

test_module #(ADDSIZE_A, DATASIZE_A) A (...);
test_module #(ADDSIZE_B, DATASIZE_B) B (...);

Inside the module A I want to instantiate module RAM_32X32.
Inside the module B I want to instantiate module RAM _32X128.

Conditional generate is your friend.

  module test_module #(parameter ASIZE=1, DSIZE=1) (...ports...);

    ... usual module-level stuff: signals, etc ...

    generate
      case (DSIZE)
        32:
          RAM_32X32 ram(...);
        128:
          RAM_32X128 ram(...);
        default:
          initial
            $display("BAD PARAM %m #(.DSIZE=%0d), \
                     DSIZE must be 32 or 128", DSIZE);
      endcase
    endgenerate

  endmodule

Strictly speaking the generate/endgenerate keywords are optional,
but I like to use them because it clarifies what I'm doing with
the special kind of "case" statement.
NOTE that it is NOT inside an initial or always block, but
appears at the top level of the module.   The error-trap
is not brilliant, but at least it will give you some
useful information if you set a parameter value for which
you haven't chosen a suitable module.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.