Guest
Hi all
i am having trouble with instantiation.
i get a SYNTAX error : token is count_up
i will point that i compile this file as top entity and 2 more files count_up.v count_down.v
not sure why this error, the design should get up or down and according to that turn on the corresponding module
module addr_gen (clk, rst_1, en, up, down, finish, bit_addr, row_addr);
input clk;
input rst_1;
//input en;
input up;
input down;
output finish;
output [3:0] bit_addr;
output [3:0] row_addr;
wire clk;
wire rst_1;
//wire en;
wire up;
wire down;
wire finish;
wire [3:0] bit_addr;
wire [3:0] row_addr
count_up U1 (.clk(clk), .rst_1(rst_1), .en(up), .finish(finish), .bit_counter_up(bit_addr), .row_counter_up(row_addr));
count_down u2(.clk, .rst_1, .en(down), .finish, .bit_counter_down,
..row_counter_down);
endmodule
i am having trouble with instantiation.
i get a SYNTAX error : token is count_up
i will point that i compile this file as top entity and 2 more files count_up.v count_down.v
not sure why this error, the design should get up or down and according to that turn on the corresponding module
module addr_gen (clk, rst_1, en, up, down, finish, bit_addr, row_addr);
input clk;
input rst_1;
//input en;
input up;
input down;
output finish;
output [3:0] bit_addr;
output [3:0] row_addr;
wire clk;
wire rst_1;
//wire en;
wire up;
wire down;
wire finish;
wire [3:0] bit_addr;
wire [3:0] row_addr
count_up U1 (.clk(clk), .rst_1(rst_1), .en(up), .finish(finish), .bit_counter_up(bit_addr), .row_counter_up(row_addr));
count_down u2(.clk, .rst_1, .en(down), .finish, .bit_counter_down,
..row_counter_down);
endmodule