C
Cor van Loos
Guest
For a very simple design I need to instantiate a lot of components. Only
two of the I/O signals of these components differ. Is there a smart way
to do this in VHDL or do I have to make a 100 copies to instatiate 100
components?
Cor
two of the I/O signals of these components differ. Is there a smart way
to do this in VHDL or do I have to make a 100 copies to instatiate 100
components?
Cor