Instantiation of edf file in verilog

[Pravin]

Hello All,

I am facing a problem while instantiating an edf file in
verilog. My IP vendor has provided me FPGA Complier's edf file & ngo
file. He has not provided .veo file.

Now I want do instantiation of this IP in verilog file using
ISE 6.1. I have tried box_type constraint. But it is not working.
Please tell me how to do this.

 

[John_H]

Pravin wrote:

Hello All,

I am facing a problem while instantiating an edf file in
verilog. My IP vendor has provided me FPGA Complier's edf file & ngo
file. He has not provided .veo file.

Now I want do instantiation of this IP in verilog file using
ISE 6.1. I have tried box_type constraint. But it is not working.
Please tell me how to do this.

Your Verilog code needs the black box module defined for a proper
compile, specifying the in/out directions and port names and sizes. The
Xilinx design flow needs a "macro search path" defined in your Translate
properties to find the .ngo file to add as part of your design, filling
in the hole left by the black box. If you're using XST, the design flow
would be HDL rather than EDIF. The .ngo would be picked up by the
synthesis through the macro search path.