T
Thomas Reinemann
Guest
Hello,
I have to instantiate a Xilinx BUFGMUX manually (VHDL), since Precision
Synthesis doesn't infer it in this situation. The signal, which is the
input for the BUFGMUX, is driven by a clock divider.
The example in
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex5.html
doesn't work.
How can I make the instantiation, but in such a way, that there is no
need for special treatment depending on simulation or synthesis.
Tom
I have to instantiate a Xilinx BUFGMUX manually (VHDL), since Precision
Synthesis doesn't infer it in this situation. The signal, which is the
input for the BUFGMUX, is driven by a clock divider.
The example in
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex5.html
doesn't work.
How can I make the instantiation, but in such a way, that there is no
need for special treatment depending on simulation or synthesis.
Tom