Instantiation of an EDF netlist within a Verilog top RTL

[rahul_fpga]

Hello Guys,

I am working with Synplify Pro. I have a RTL wrapper in Verilog where
module is instantiated. But this module is available as an EDF netlist. Ho
can I include this EDF netlist in my Synplify project so that it can b
integrated with the wrapper RTL without any compilation error?

Best regards,
Rahul



---------------------------------------
Posted through http://www.FPGARelated.com

 

[maxascent]

Hello Guys,

I am working with Synplify Pro. I have a RTL wrapper in Verilog where a
module is instantiated. But this module is available as an EDF netlist
How
can I include this EDF netlist in my Synplify project so that it can be
integrated with the wrapper RTL without any compilation error?

Best regards,
Rahul



---------------------------------------
Posted through http://www.FPGARelated.com

Just add a blackbox synthesis directive to the wrapper and everything wil
be fine.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com

 

[shyam]

On May 27, 1:05 pm, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

Hello Guys,

I am working with Synplify Pro. I have a RTL wrapper in Verilog where a
module is instantiated. But this module is available as an EDF netlist.
How
can I include this EDF netlist in my Synplify project so that it can be
integrated with the wrapper RTL without any compilation error?

Best regards,
Rahul

---------------------------------------            
Posted throughhttp://www.FPGARelated.com

Just add a blackbox synthesis directive to the wrapper and everything will
be fine.

Jon        

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Additionally, IO insertion should be disabled when the EDIF netlist
is generated.
If IO insertion isn't disabled, Synplify Pro treats the inputs and
outputs on the RTL
used for edif netlist as IOs and instantiates IO pads on it.

Thanks
Shyam