Instantiating VHDL component with integer ports in Verilog m

[Paul Urbanus]

I have inherited a design with a component written in VHDL. This
component has some ports which are constrained integers, and one port is
a user defined type. This component is instantiated in verilog module.
When I try and run the verilog module, ModelSim (ver 6.1f) complains as
follows:

# ** Fatal: (vsim-3362) The type of VHDL port 'regfilecontrol' is
invalid for Verilog connection (15th connection).

Here is the offending VHDL port definition
regFileControl : out tRegFile(sizeOfRegFile+startOfRegFile-1
downto startOfRegFile);

Here's the corresponding actual port parameter in the verilog code where
the offending component is instantiated.

reg [(kMemMapSize*8)-1:0] ctrlReg;


These ports on the VHDL components also generated the same error.

readDelay : in integer range 0 to 7; -- specifies how
long to wait before returning data
secondaryDelay : in integer range 0 to 7; -- specifies
how long to wait before reading data from the secondary PLD

I fixed the above problem by changing the port type to
std_logic_vector(2 downto 0)

It appears to me that ModelSim will only allow a limited subset of
possible VHDL port types to be mapped to an upper level verilog module -
namely, std_logic or std_logic vector

Any suggestion on how I can circumvent this without massively changing
the existing VHDL code, which is not an option. The VHDL module in
question is actually a configuration interface to a proprietary bus
interface. I am replacing it with some stub code with literal register
values specified in my code, as that is sufficient for the functionality
I am developing. My goal was to replace their fully functional module
with my stub module, while maintaining the same port interface
structure. Complicating this is the presence of a package file which
contains the port prototypes for many of the modules - not just the
problem module.

Any ideas or comments from this verilog noob?

TIA - Urb


keeping all of tehI am actually replacing the customer's VHDL module

 

[Mike Treseler]

Paul Urbanus wrote:

It appears to me that ModelSim will only allow a limited subset of
possible VHDL port types to be mapped to an upper level verilog module -
namely, std_logic or std_logic vector

True.

Any suggestion on how I can circumvent this without massively changing
the existing VHDL code, which is not an option.

I would write a vhdl wrapper entity that
instances the untouchable vhdl module
and converts the problem ports to std_logic_vector
and just passes the other ports through.

Complicating this is the presence of a package file which
contains the port prototypes for many of the modules - not just the
problem module.

The package is only needed to compile the component
and the wrapper. The verilog part won't use it.

Any ideas or comments

The wrapper will have to be modified if the
interface configuration is changed.
Good luck.

-- Mike Treseler

 

[HT-Lab]

"Paul Urbanus" <urbpublic@hotmail.com> wrote in message
news:s9udnTMwzKeQfxjUnZ2dnUVZ_g6WnZ2d@speakeasy.net...

I have inherited a design with a component written in VHDL. This component
has some ports which are constrained integers, and one port is a user
defined type. This component is instantiated in verilog module. When I try
and run the verilog module, ModelSim (ver 6.1f) complains as follows:

# ** Fatal: (vsim-3362) The type of VHDL port 'regfilecontrol' is invalid
for Verilog connection (15th connection).

Here is the offending VHDL port definition
regFileControl : out tRegFile(sizeOfRegFile+startOfRegFile-1 downto
startOfRegFile);

Here's the corresponding actual port parameter in the verilog code where
the offending component is instantiated.

reg [(kMemMapSize*8)-1:0] ctrlReg;


These ports on the VHDL components also generated the same error.

readDelay : in integer range 0 to 7; -- specifies how long
to wait before returning data
secondaryDelay : in integer range 0 to 7; -- specifies how
long to wait before reading data from the secondary PLD

I fixed the above problem by changing the port type to std_logic_vector(2
downto 0)

It appears to me that ModelSim will only allow a limited subset of
possible VHDL port types to be mapped to an upper level verilog module -
namely, std_logic or std_logic vector

You are out of luck wrt the user defined types (unless you are using
SystemVerilog?) but the constrained integer should be supported in a later
version.

From the 6.4c manual:

VHDL Instantiation Criteria Within Verilog
You can instantiate a VHDL design unit within Verilog or SystemVerilog if it
meets the following criteria:
.. The design unit is an entity/architecture pair or a configuration.
.. The entity ports are of type: bit, bit_vector, enum, integer, natural,
positive, real,
shortreal; std_logic, std_ulogic, std_logic_vector, std_ulogic_vector,
vl_ulogic,
vl_ulogic_vector, or their subtypes; unconstrained arrays; nested records;
and records
with fields of type integer, real, enum, and multi-dimensional arrays.
The port clause may have any mix of these types. Multi-dimensional arrays of
these
support types are also supported.
.. The generics are of type bit, bit_vector, integer, real, std_logic,
std_logic_vector,
vl_logic, vl_logic_vector, time, physical, enumeration, or string.
String is the only composite type allowed.

If you are using SystemVerilog you *may* be able to also resolve the custom
type by importing the VHDL package and compiling your vhdl code with
the -mixedsvvh option.

Hans
www.ht-lab.com

Any suggestion on how I can circumvent this without massively changing the
existing VHDL code, which is not an option. The VHDL module in question is
actually a configuration interface to a proprietary bus interface. I am
replacing it with some stub code with literal register values specified in
my code, as that is sufficient for the functionality I am developing. My
goal was to replace their fully functional module with my stub module,
while maintaining the same port interface structure. Complicating this is
the presence of a package file which contains the port prototypes for many
of the modules - not just the problem module.

Any ideas or comments from this verilog noob?

TIA - Urb


keeping all of tehI am actually replacing the customer's VHDL module