Instantiating subblock signals with VHDL

[arkaitz]

Hi all,

This question might obvious, but I cannot find any other way to
instatiate signals from a top of a design for simulation purposses.

What I usually do is to add those signals as ports in each entity
beginning from the bottom of the design and continuing the hierarchy
until I arrive to the top. In order not to consider them in the
synthesis I add "synthesis translate off/on" comments.

Here you are an example:

Imagine that I want to instantiate the internal signal of the
subblock1 from the top

entity top is
port(
-- synthesis translate off
tb_out : out std_logic;
-- synthesis translate on
...
);
end top;

architecture arch of top is
begin

uut: subblock1
port map(
-- synthesis translate_off
internal => tb_out,
-- synthesis translate_on
...
);
end;

Then I instantiate the top in the same way from the testbench.

I know that in verilog there is another way just with something like
this.

"top.subblock1.internal"

I would be glad is someone could help.

Thanks in advance,

Arkaitz.

 

[Srinivasan Venkataramanan]

Hi,
VHDL doesn't allow white box probing in the language and hence is this
issue. Having said that, many simulators provide through their APIs a way to
do this. You didn't mention which simulator(s) you are using, AFAIK NCSIM,
Modelsim & Aldec supports such APIs. The down side is that your TB code
tends to become simulator dependent. I recently uploaded a simple package to
avoid this, you may want to take a look at that, see

http://www.noveldv.com/eda/probe.zip

HTH,
Srinivasan

"arkaitz" <arkagaz@yahoo.com> wrote in message
news:c1408b8c.0405100720.26a061da@posting.google.com...

Hi all,

This question might obvious, but I cannot find any other way to
instatiate signals from a top of a design for simulation purposses.

What I usually do is to add those signals as ports in each entity
beginning from the bottom of the design and continuing the hierarchy
until I arrive to the top. In order not to consider them in the
synthesis I add "synthesis translate off/on" comments.

Here you are an example:

Imagine that I want to instantiate the internal signal of the
subblock1 from the top

entity top is
port(
-- synthesis translate off
tb_out : out std_logic;
-- synthesis translate on
...
);
end top;

architecture arch of top is
begin

uut: subblock1
port map(
-- synthesis translate_off
internal => tb_out,
-- synthesis translate_on
...
);
end;

Then I instantiate the top in the same way from the testbench.

I know that in verilog there is another way just with something like
this.

"top.subblock1.internal"

I would be glad is someone could help.

Thanks in advance,

Arkaitz.

 

[Mike Treseler]

arkaitz wrote:

This question might obvious, but I cannot find any other way to
instantiate signals from a top of a design for simulation purposes.

Consider instancing all of your sub-entities,
directly into a testbench and wiring
them up with testbench signals.
Now one level of structural wiring
is directly visible.

After you get this working, add an instance
of the real top entity into the same testbench
to verify that it works the same.

-- Mike Treseler

 

[Jeff Cunningham]

I believe in VHDL you can create in effect a global signal by declaring
it in a package and then including that package in all the places you
want the scope of that signal to go. I think most synthesizers will
choke on it, but for simulation/testbench it might be workable.
-JCC