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I have a design with too many global clocks which ISE automatically adds.
Some of these clocks are slow and feed into relatively small areas of logic.
Is there a way I can specify these clocks to be non-global?
Many thanks. I thought all was going well until Translate. UnfortunatelyOn Tue, 2010-08-10 at 13:15 +0100, Fredxx wrote:
I have a design with too many global clocks which ISE automatically
adds.
Some of these clocks are slow and feed into relatively small areas
of logic.
Is there a way I can specify these clocks to be non-global?
Hi,
try to use BUFR.
cheers
ben
Hm, to bad. Then you have to reduce your clocks and for example use clockMany thanks. I thought all was going well until Translate. Unfortunately
Spartan 3A's don't support the BUFR primitive!
Many thanks. I used the attribute buffer_type = "none", but it seem toOn Aug 10, 8:38 am, Benjamin Krill <b...@codiert.org> wrote:
Many thanks. I thought all was going well until Translate.
Unfortunately Spartan 3A's don't support the BUFR primitive!
Hm, to bad. Then you have to reduce your clocks and for example use
clock enables for the slower logic parts.
Some spartan 3A parts have left or right half clock regions. If the
buffer for these is not called a BUFR there should be some other
way to use it.
Also for small regions it is possible to attach a constraint to
the clock net (BUFFER_TYPE = NONE if I remember correctly)
to remove the BUFG. Then you should add a USELOWSKEWNETS
(IIRC) attribute and make sure your timing analysis includes hold
time. If your clock is very slow, you can also play games to avoid
hold time errors like always going from rising edge to falling edge.
I'll second the clock enables. A common techinique is to use a singleMany thanks. I thought all was going well until Translate. Unfortunately
Spartan 3A's don't support the BUFR primitive!
Hm, to bad. Then you have to reduce your clocks and for example use clock
enables for the slower logic parts.
Some spartan 3A parts have left or right half clock regions. If theMany thanks. I thought all was going well until Translate. Unfortunately
Spartan 3A's don't support the BUFR primitive!
Hm, to bad. Then you have to reduce your clocks and for example use clock
enables for the slower logic parts.
I can't comment on the error, but be careful with capturing clocks toGabor wrote:
On Aug 10, 8:38 am, Benjamin Krill <b...@codiert.org> wrote:
Many thanks. I thought all was going well until Translate.
Unfortunately Spartan 3A's don't support the BUFR primitive!
Hm, to bad. Then you have to reduce your clocks and for example use
clock enables for the slower logic parts.
Some spartan 3A parts have left or right half clock regions. If the
buffer for these is not called a BUFR there should be some other
way to use it.
Also for small regions it is possible to attach a constraint to
the clock net (BUFFER_TYPE = NONE if I remember correctly)
to remove the BUFG. Then you should add a USELOWSKEWNETS
(IIRC) attribute and make sure your timing analysis includes hold
time. If your clock is very slow, you can also play games to avoid
hold time errors like always going from rising edge to falling edge.
Many thanks. I used the attribute buffer_type = "none", but it seem to
remove the offending clock altogether from the design. Not quite what I had
intended. I then had a myraid more errors.
In the end I resorted to removing the offending clocks and capture its edge
with a high speed clock. All seemed well until Map when I got:
FATAL_ERROR:3:xstphs.c:71:1.11.10.1 - Physical Synthesis Failed. Process
will
terminate. For technical support on this issue, please open a WebCase
with this project attached athttp://www.xilinx.com/support.- Hide quoted text -
- Show quoted text -