A
Adaeze
Guest
Hi,
I am writing a veriloga model of system which is a combination of an amplifier and a filter. I already have the veriloga model for the ampilifier so I wanted to use an instance of this model for the overall veriloga model of the system.
From veriloga manual, it appears that I have to write the amplifier's veriloga within the same file for my overall system and then instantiate it [see example below]:
module comparator(cout, inp, inm);
output cout;
input inp, inm;
electrical cout, inp, inm;
parameter real td = 1n, tr = 1n, tf = 1n;
analog begin
@cross(V(inp) - V(inm), 0)
V(cout) <+ transition((V(inp) > V(inm)) ? 1 : 0, td, tr, tf);
end
endmodule
module integrator(out, in);
output out;
input in;
electrical in, out;
parameter real gain = 1.0;
parameter real ic = 0.0;
analog begin
V(out) <+ gain*idt(V(in), ic);
end
endmodule
module sigmadelta(out, ref, in);
output out;
input ref, in;
comparator C1(.cout(aa0), .inp(in), .inm(aa2));
integrator #(1.0) I1(.out(aa1), .in(aa0));
comparator C2(out, aa1, ground);
d2a #(.width(1)) D1(aa2, ref, out); // A D/A converter
endmodule
I tried doing this using 'name port connection' but it gives me a syntax error in the line where I instantiated the amplifier. I did it very similar to the code above After some intense reading, I realized that leaving any ports unconnected when using the name port connection results in an error. My overall system has 3 more additional ports than my amplifier so I decided to use the ordered port connection which seemed to allow me to leave some ports unconnected. Now it gives me this error:
Encountered ordered parameter override lists. The software does not support this feature. Use named lists instead.
I am using the Cadence IC6.1.6 version
Please I would appreciate any useful advice on how to instantiate modules in Verilog-A or a link to a website that explains it well.
Regards,
Adaeze
I am writing a veriloga model of system which is a combination of an amplifier and a filter. I already have the veriloga model for the ampilifier so I wanted to use an instance of this model for the overall veriloga model of the system.
From veriloga manual, it appears that I have to write the amplifier's veriloga within the same file for my overall system and then instantiate it [see example below]:
module comparator(cout, inp, inm);
output cout;
input inp, inm;
electrical cout, inp, inm;
parameter real td = 1n, tr = 1n, tf = 1n;
analog begin
@cross(V(inp) - V(inm), 0)
V(cout) <+ transition((V(inp) > V(inm)) ? 1 : 0, td, tr, tf);
end
endmodule
module integrator(out, in);
output out;
input in;
electrical in, out;
parameter real gain = 1.0;
parameter real ic = 0.0;
analog begin
V(out) <+ gain*idt(V(in), ic);
end
endmodule
module sigmadelta(out, ref, in);
output out;
input ref, in;
comparator C1(.cout(aa0), .inp(in), .inm(aa2));
integrator #(1.0) I1(.out(aa1), .in(aa0));
comparator C2(out, aa1, ground);
d2a #(.width(1)) D1(aa2, ref, out); // A D/A converter
endmodule
I tried doing this using 'name port connection' but it gives me a syntax error in the line where I instantiated the amplifier. I did it very similar to the code above After some intense reading, I realized that leaving any ports unconnected when using the name port connection results in an error. My overall system has 3 more additional ports than my amplifier so I decided to use the ordered port connection which seemed to allow me to leave some ports unconnected. Now it gives me this error:
Encountered ordered parameter override lists. The software does not support this feature. Use named lists instead.
I am using the Cadence IC6.1.6 version
Please I would appreciate any useful advice on how to instantiate modules in Verilog-A or a link to a website that explains it well.
Regards,
Adaeze