Instantiating a module multiple times in Vlog '01

[Andrew Whyte]

I am using Verilog 2001 and am trying to use a generate loop to create a
number of instances of a module - see code below. The problem is that
ModelSim fails with a stack trace error (code 211) with the only line
mentioned being the declaration of the for loop constraints. My synth
tools will happily synthesise a number of registers for this bit of
code.

I'm using ModelSim 5.8c (PE and SE), but have tried previous versions
too and it still fails - is it a known bug? I can't use ModelSim v6.

Cheers,

Andrew

---- Begin code snippet ----

module reg_test(d, c, q);

parameter width = 32;

input wire [width-1 : 0] d;
input wire c;
output wire [width-1 : 0] q;

generate
genvar i;

for (i=0; i< width; i=i+1)
begin : gen_regs

reg_fd simple_reg (.clk(c), .ce(), .ainit(), .aclr(), .aset(),
..sinit(), .sclr(), .sset(), .d(d), .q(q));

defparam simple_reg.width = 1,
simple_reg.ainit_val = 0,
simple_reg.sinit_val = 0,
simple_reg.sync_priority = 0,
simple_reg.sync_enable = 0,
simple_reg.has_ce = 0,
simple_reg.has_aclr = 0,
simple_reg.has_aset = 0,
simple_reg.has_ainit = 0,
simple_reg.has_sclr = 0,
simple_reg.has_sset = 0,
simple_reg.has_sinit = 0;
end
endgenerate

endmodule

---- End code snippet ----

 

[Jim Wu]

I don't know why ModelSim has problem with the code, but one thing I'd
suggest is overwrite parameters as part of module instantiation instead of
using "defparm". eg.

reg_fd #(.simple_reg (1)) simple_reg (.clk(c), .ce(), .ainit(), .aclr(),
..aset(),
.sinit(), .sclr(), .sset(), .d(d), .q(q));

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



"Andrew Whyte" <andrew.whyte@xilinx.com> wrote in message
news:420B8357.EB5CABFA@xilinx.com...

I am using Verilog 2001 and am trying to use a generate loop to create a
number of instances of a module - see code below. The problem is that
ModelSim fails with a stack trace error (code 211) with the only line
mentioned being the declaration of the for loop constraints. My synth
tools will happily synthesise a number of registers for this bit of
code.

I'm using ModelSim 5.8c (PE and SE), but have tried previous versions
too and it still fails - is it a known bug? I can't use ModelSim v6.

Cheers,

Andrew

---- Begin code snippet ----

module reg_test(d, c, q);

parameter width = 32;

input wire [width-1 : 0] d;
input wire c;
output wire [width-1 : 0] q;

generate
genvar i;

for (i=0; i< width; i=i+1)
begin : gen_regs

reg_fd simple_reg (.clk(c), .ce(), .ainit(), .aclr(), .aset(),
.sinit(), .sclr(), .sset(), .d(d), .q(q));

defparam simple_reg.width = 1,
simple_reg.ainit_val = 0,
simple_reg.sinit_val = 0,
simple_reg.sync_priority = 0,
simple_reg.sync_enable = 0,
simple_reg.has_ce = 0,
simple_reg.has_aclr = 0,
simple_reg.has_aset = 0,
simple_reg.has_ainit = 0,
simple_reg.has_sclr = 0,
simple_reg.has_sset = 0,
simple_reg.has_sinit = 0;
end
endgenerate

endmodule

---- End code snippet ----