Instantiate primitives in for-generate?

[George Mercury]

Hello,
I'm trying to do a really generic desing of a DDR-Controller. To do so,
I need to instantiate a variable number of primitives. So I was
wondering, if there is some way that I could instantiate primitives in
a for-generate loop?

Best Regards,
George

 

[john Doef]

George Mercury a écrit :

Hello,
I'm trying to do a really generic desing of a DDR-Controller. To do so,
I need to instantiate a variable number of primitives. So I was
wondering, if there is some way that I could instantiate primitives in
a for-generate loop?
Primitives is not a VHDL concept. Please explain what is a primitive.

For sure, in a for-generate loop, you can put any concurrent
statements, such
as component instantiation or processes.

JD.

 

[jtw]

Yes, George, you can. My perspective on 'primitive'--well, I'm used to it
being the vendor-specific library elements. The 'leaf node' components
instantiated in your design. Call them what you will.

An example from: http://www.noveldv.com/verif/hdl_faq/FAQ00005.htm

f_l : for i in 0 to 3 generate
Comp : Nor2 port map (I1 => A(i),
I2 => B(i),
O => S(i));
end generate;

In this example, it is a fixed number. However, if you define a constant to
be equal to a given generic, it will be compile-time variable (but still
run-time fixed.)

If you want run-time variability, you still must design the underlying
structure to support the worst case.

JTW

"john Doef" <john_doef@yahoo.com> wrote in message
news:1122539047.414218.163120@g14g2000cwa.googlegroups.com...


George Mercury a écrit :

Hello,
I'm trying to do a really generic desing of a DDR-Controller. To do so,
I need to instantiate a variable number of primitives. So I was
wondering, if there is some way that I could instantiate primitives in
a for-generate loop?
Primitives is not a VHDL concept. Please explain what is a primitive.

For sure, in a for-generate loop, you can put any concurrent
statements, such
as component instantiation or processes.

JD.