Instantiate modules with the same name from two different fi

[Travis]

Hi, I've got two modules with the same name, in different files, in
the same project.

I'd like to instantiate them in my testbench to create a miter, but
I'd really rather not just
change the name of one of them.

Is there a more elegant solution? I was trying to use the . (dot)
operator as follows:
{file one}.module
{file two}.module

but Modelsim is not happy with this.

Thanks all,
Travis

 

[Mike314]

On Mar 15, 4:18 pm, Travis <TRAy...@gmail.com> wrote:

Hi, I've got two modules with the same name, in different files, in
the same project.

I'd like to instantiate them in my testbench to create a miter, but
I'd really rather not just
change the name of one of them.

Is there a more elegant solution? I was trying to use the . (dot)
operator as follows:
{file one}.module
{file two}.module

but Modelsim is not happy with this.

Thanks all,
Travis

Unfortunately (or better say fortunately) all modules must have a
unique name. Just rename your module like "file_one_module" and
"file_two_module" and make a clean instantiation.

Regards,
Michael

 

[Jonathan Bromley]

On Sat, 14 Mar 2009 22:18:54 -0700 (PDT), Travis wrote:

Hi, I've got two modules with the same name, in different files, in
the same project.

I'd like to instantiate them in my testbench to create a miter, but
I'd really rather not just
change the name of one of them.

You could insert a `uselib directive before each:

module TopLevel;
// wires etc go here as usual

`uselib file=file1.v
mymod inst1(ports,ports,ports);

`uselib file=file2.v
mymod inst2(moreports, moreports);

endmodule

Now you compile TopLevel but DO NOT include "file1.v"
and "file2.v" in the compilation. Verilog will discover
the undefined modules, and search for them in the
specified files.

You can also do it with the Verilog-2001 library/config
mechanism, if you are sufficiently brave
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Sun, 15 Mar 2009 09:30:22 +0000, Jonathan Bromley wrote:

module TopLevel;
// wires etc go here as usual

`uselib file=file1.v
mymod inst1(ports,ports,ports);

`uselib file=file2.v
mymod inst2(moreports, moreports);

endmodule

Now you compile TopLevel but DO NOT include "file1.v"
and "file2.v" in the compilation. Verilog will discover
the undefined modules, and search for them in the
specified files.

WHOOPS, sorry, it's been a while since I did this and I
forgot something: YOU MUST add the option -compile_uselibs
on the vlog command line, so that ModelSim's verilog
compiler will scan the additional files. Something like

vlog -compile_uselibs TopLevel.v
vsim TopLevel

There are various other possible methods in which
you compile the various sub-module files into
their own libraries. See the ModelSim command
reference on vlog for more details.

The `uselib mechanism only works correctly if the
sub-module does NOT exist in the "work" library
at the time when you do the compile.

Apologies.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.