Instances

[Luiz Gustavo]

In Verilog can I have two modules working independently, but
interconnect? Or, may I have one "big" module and instance the other
module inside the big? Or the two?

 

[terabits]

On Feb 7, 4:34 am, "Luiz Gustavo" <luizval...@gmail.com> wrote:

In Verilog can I have two modules working independently, but
interconnect? Or, may I have one "big" module and instance the other
module inside the big? Or the two?

Either is possible it depends on ur requirement.
for example you have a 2:1 mux you want to develop some big one..then
you can instantiate this 2:1 mux in ur big mux.
suppose you have a masters and arbiter,you need not have a big module
instantiating masters and arbiter there you can have them
independently running and connect them.
if it doesn't help , can you give the specific requirement.?

rgds

 

[Luiz Gustavo]

On Feb 7, 3:17 pm, "terabits" <tera.b...@gmail.com> wrote:

On Feb 7, 4:34 am, "Luiz Gustavo" <luizval...@gmail.com> wrote:

In Verilog can I have two modules working independently, but
interconnect? Or, may I have one "big" module and instance the other
module inside the big? Or the two?

Either is possible it depends on ur requirement.
for example you have a 2:1 mux you want to develop some big one..then
you can instantiate this 2:1 mux in ur big mux.
suppose you have a masters and arbiter,you need not have a big module
instantiating masters and arbiter there you can have them
independently running and connect them.
if it doesn't help , can you give the specific requirement.?

rgds

My application is exactly that!!! I want a master to comunicate with
one slave through a SPI interface...

Thanks