Instances

[Luiz Gustavo]

In Verilog can I have two modules working independently, but
interconnect? Or, may I have one "big" module and instance the other
module inside the big?

 

Luiz Gustavo wrote:

In Verilog can I have two modules working independently, but
interconnect? Or, may I have one "big" module and instance the other
module inside the big?

If you have two top-level modules, there is no way to
interconnect them through their ports.

If these modules are supposed to be peers, then you
should have a top-level module for your design that
instantiates the two modules and connects them
together.

 

[terabits]

On Feb 8, 11:57 am, s...@cadence.com wrote:

Luiz Gustavo wrote:
In Verilog can I have two modules working independently, but
interconnect? Or, may I have one "big" module and instance the other
module inside the big?

If you have two top-level modules, there is no way to
interconnect them through their ports.

What do you mean by "not way to interconnect 'em thru ports" ,
interconnecting them comes only with a higher module on top of them..
when u r saying two modules they are peers and are communicationg
using a tb or a big module on top of them..

well probly from his question he might be asking....is it better to
have a mast_arb module which instantiates a master and arbiter inside,
i said there is no need, you can have a tb where u can instantiate a
master a arbiter and what not.....
then connect the signals accordingly in the topmodule.

If these modules are supposed to be peers, then you
should have a top-level module for your design that
instantiates the two modules and connects them
together.