instances of entities vs components

[Andy Peters]

File this under "VHDL philosophy."

Given a top-level entity that instantiates some lower-level entites, do
you:

a) instantiate the lower-level modules as entities, e.g.,

u_foo : entity work.foo
port map ( signals );

b) instantiate the lower-level modules as components, e.g.,

u_foo : component foo
port map (signals );

The advantage of a) is that you don't have to type the lower-level
entity's port interface declaration in your architecture. The
disadvantages of a) is that you don't see that entity's interfaces in
your architecture, and you have to ensure that you compile the
lower-level entities before the higher-level ones.

The advantage of b) is that it's clear what signals the lower-level
entity needs. The disadvantage is that if you change the interface to
the lower-level entity (in its source file), you have to make sure that
you change the component declaration in your higher-level module's
architecture. Keeping these in sync could be a problem.

Of course, you could package the component and use the package in your
top-level design, but then you still don't see the port declarations in
the top-level module.

And do you create separate files for the component packages, which
means you have to maintain them if the interface changes, but you don't
have to recompile the top-level if the lower-level changes? (Yes, I
use makefiles, which helps.)

Oy, it's all confusing. Thoughts ??

-a