Inputting an array of constants in a module

[thomasc]

Is it possible to pass or refer to an array of constants in multiple
modules?

I need to input an array of constants across multiple modules so it can be
referred to by the modules. The array consists of 16 8-bit elements and
needs to be used in a procedural block. But when I tried to do so, it
generated an error.

First, I declared the array as input into a module. However while
compiling, ModelSim says <Illegal reference to net array "array_table">.

So I declared the input array as wire in the module to use it in a
procedural block and compiled again. This time ModelSim says "#'Port' must
not be declared to be an array: array_table."

Any comment will be a help for me.
Thanks!

*I will eventually have to synthesize this project. So please keep that in
mind when you reply.

 

[Rob Dekker]

Constants are best modeled with parameters or `define's, especially if you intent to use this design for synthesis.

Unfortunately, Verilog 95 and Verilog 2001 do not allow parameters to be more than 1 dimension in size
(so you can model only a single-dimensional array of bit constants).
System Verilog does allow multi-dimensional parameters, and also has a 'constant' data type.
However, System Verilog is not yet supported in many tools.

Since you want to use these constants all over different modules, `defines are probably the best solution
if you stay within Verilog 95/2001.
I suggest that you use `defines to give your constants some names, and then use these constants in the design.
You might need to have a long list of constants and be creative/constistent in the names you give them, so that you
don't get confused yourself when you use them.

Rob

"thomasc" <altecsplinter@hotmail.com> wrote in message news:94af47f3e7b65b086d48fb803063f591@localhost.talkaboutprogramming.com...

Is it possible to pass or refer to an array of constants in multiple
modules?

I need to input an array of constants across multiple modules so it can be
referred to by the modules. The array consists of 16 8-bit elements and
needs to be used in a procedural block. But when I tried to do so, it
generated an error.

First, I declared the array as input into a module. However while
compiling, ModelSim says <Illegal reference to net array "array_table">.

So I declared the input array as wire in the module to use it in a
procedural block and compiled again. This time ModelSim says "#'Port' must
not be declared to be an array: array_table."

Any comment will be a help for me.
Thanks!

*I will eventually have to synthesize this project. So please keep that in
mind when you reply.

 

[Berty]

if you want to keep your code the way it is and pass two dimention
array you can always trasfer it to single long vector and open it again
at the destination.

have fun.