T
thomasc
Guest
=how to give inputs to FPGA, how to observe outputs from FPGA=
Hi,
My verilog design has been synthesized and has passed post-PAR simulation.
And I understand how to load my design on FPGA(particularly, Xilinx
Spartan-3 XC3S400). Now I want to give inputs to the design on FPGA and
observe outputs out of it. But I have no idea how I can do it.
1) giving inputs: While doing simulations on PC, I could give inputs to
the design using a testbench file. But I have no idea at all how to give
inputs to the FPGA. Please let me know how to do it. (*I'm using Xilinx
ISE 6.3i)
2) observing outputs: My understanding is that I can assign a pin for each
bit of the output values by editing the UCF file and that's waht I did. I
heard that, in order to observe outputs, I needed to connect an
oscilloscope to each of the pins. Is this correct? Please let me know
whether this is correct and If there is a better or easier way to do it.
Thanks much in advance!
Hi,
My verilog design has been synthesized and has passed post-PAR simulation.
And I understand how to load my design on FPGA(particularly, Xilinx
Spartan-3 XC3S400). Now I want to give inputs to the design on FPGA and
observe outputs out of it. But I have no idea how I can do it.
1) giving inputs: While doing simulations on PC, I could give inputs to
the design using a testbench file. But I have no idea at all how to give
inputs to the FPGA. Please let me know how to do it. (*I'm using Xilinx
ISE 6.3i)
2) observing outputs: My understanding is that I can assign a pin for each
bit of the output values by editing the UCF file and that's waht I did. I
heard that, in order to observe outputs, I needed to connect an
oscilloscope to each of the pins. Is this correct? Please let me know
whether this is correct and If there is a better or easier way to do it.
Thanks much in advance!