inputs/outputs in verilog primitives

Hi,

Do you know if inputs/output of verilog primitives can be instanced by
name instead of by order?

for example:

can I write:

not n1(.out(w1),.in(w2)) or not n1(.in(w2),.out(w1))

instead of:

not n1(w1,w2) ?

 

paziam1@gmail.com wrote:

Hi,

Do you know if inputs/output of verilog primitives can be instanced by
name instead of by order?

No. The ports of built-in primitives do not have names that can be
used.
You have to connect them by position.