inputs/outputs in verilog primitives

Guest
Hi,

Do you know if inputs/output of verilog primitives can be instanced by
name instead of by order?

for example:

can I write:

not n1(.out(w1),.in(w2)) or not n1(.in(w2),.out(w1))

instead of:

not n1(w1,w2) ?
 
On 15 Apr 2007 06:54:08 -0700, paziam1@gmail.com wrote:

Hi,

Do you know if inputs/output of verilog primitives can be instanced by
name instead of by order?

for example:

can I write:

not n1(.out(w1),.in(w2)) or not n1(.in(w2),.out(w1))

instead of:

not n1(w1,w2) ?
No. Ordered connection only - outputs first.

Also, it's not essential to have an instance name on a
primitive - so, for example:

not (w1, w2);

is OK.

Is there any special reason why you prefer that over
assign w1 = ~w2;
??
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Apr 15, 5:49 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On 15 Apr 2007 06:54:08 -0700, pazi...@gmail.com wrote:

Hi,

Do you know if inputs/output of verilog primitives can be instanced by
name instead of by order?

for example:

can I write:

not n1(.out(w1),.in(w2)) or not n1(.in(w2),.out(w1))

instead of:

not n1(w1,w2) ?

No. Ordered connection only - outputs first.

Also, it's not essential to have an instance name on a
primitive - so, for example:

not (w1, w2);

is OK.

Is there any special reason why you prefer that over
assign w1 = ~w2;
??
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


Thanks.
There is no reason, just someone asked me about it...
 

Welcome to EDABoard.com

Sponsor

Back
Top