input delay setting for Design Compiler.

[Essen]

Hi all,

In my design, input port A will be clocked by input clock
CLKA, but it is output of a flip-flop, clocked by CLKB,
in design B. CLKA and CLKA have the same frequency but
different phase. How to set input_delay's reference clock
on port A in Design Compiler? (ie, set_input_delay -clock ??)

What if CLKA(internal clock) is synchronized by input
clock CLKC? (eg, CLKC=60MHz, CLKA=120MHz)

What if input port A is combined with other signal then
output to output port B. There is no filp-flop in the
path. Then the same question?

What if input port A will be clocked by CLKA and CLKD in
two different path. CLKA and CLKD have the same frequency
but different phase.The same question?

Thanks for any suggestions!