P
Patrick Twomey
Guest
I am trying to send live video data (a data rate of 160 Mbps) over a
10m cable between two FPGAs. I am using a pair of Gigastar Piggyback
boards with Transmitter and Receiver (ING_TRC) to achieve this. Has
anyone used these boards to acieve this?
Also, the transmitter and receiver work on 33 MHz clock so as to send
up to a data rate of 1.32 Gbps. I have this clock as an read clock to
an asynchronous fifo (the write clock to the fifo is 13.5 MHz and is
generated on the FPGA). Does this 33 MHz external clock have to bo a
global clock buffer or will a standard IBUF will do?
10m cable between two FPGAs. I am using a pair of Gigastar Piggyback
boards with Transmitter and Receiver (ING_TRC) to achieve this. Has
anyone used these boards to acieve this?
Also, the transmitter and receiver work on 33 MHz clock so as to send
up to a data rate of 1.32 Gbps. I have this clock as an read clock to
an asynchronous fifo (the write clock to the fifo is 13.5 MHz and is
generated on the FPGA). Does this 33 MHz external clock have to bo a
global clock buffer or will a standard IBUF will do?