inout ports?

[CupOfWater]

Hi, I have some questions over the use of inout ports. Say I have a
closed source module (my_mod) that contains an 8 bit command i/o bus
declared as inout. Now in the module one level higher I'm trying to
communicate with F0. I'm using an 8 bit bus and an 8 bit register for
this purpose. I want any command written to the register to be
communicated to F0; and I want any command written out by F0 to be
available in the register. What kind of support does verilog have for
what I need?

here are some code to show what I mean:
module tb;
reg [7:0] io;
wire [7:0] io_status;
my_mod F0(
.io(io_status)
);
initial begin
io = 8'hxx;
statusread; // this is a task
#400 $stop;
end
/*
always@(io_status)
io = io_status; //syntax error
*/
assign io_status = io;

....
endmodule

now it appears that if I do:
io = 8'ha0;
then the module sees A0 on the bus and does some stuff. But I can't
seem to get a response from the module. From just what I have here,
do I have enough to do what I want to do?

Thanks in advance.

-K

 

[Steven Sharp]

asiandoof@hotmail.com (CupOfWater) wrote in message news:<e0c9495d.0308251025.10e9e552@posting.google.com>...

Hi, I have some questions over the use of inout ports. Say I have a
closed source module (my_mod) that contains an 8 bit command i/o bus
declared as inout. Now in the module one level higher I'm trying to
communicate with F0. I'm using an 8 bit bus and an 8 bit register for
this purpose. I want any command written to the register to be
communicated to F0; and I want any command written out by F0 to be
available in the register. What kind of support does verilog have for
what I need?


now it appears that if I do:
io = 8'ha0;
then the module sees A0 on the bus and does some stuff. But I can't
seem to get a response from the module. From just what I have here,
do I have enough to do what I want to do?

As in real hardware, if you have multiple drivers of a bus, you will
need to have logic to determine which driver is active at any given
time. If multiple drivers are active at the same time, you will have
driver contention, which will prevent values from being transmitted
properly and can damage the hardware.

The most common way of inactivating a driver is to tristate it, putting
it into a Hi-Z state so that another driver can drive the bus. This
requires extra logic to determine which driver should be enabled. Then
you can set the driver to Hi-Z when not enabled, using the continuous
assignment (or bufif primitives).

assign stat_io = enable ? io : 8'hzz;

If you are synthesizing the design, this will only work if the technology
you are using supports tristating or some other mechanism for allowing
multiple drivers. Otherwise, you can't have a bidirectional bus.

It is a good idea to understand hardware before trying to write Verilog.

 

[black]

inout stat_io;
input enable , io ;
output another_o;
assign stat_io = enable ? io : 8'hzz;

when the stat_io works as input ,does it need enable ,just like:
assign another_o = enable ?~ stat_io:8'hzz;
or just :
assign another_o =~stat_io ;
which one is correct?
Thanks a lot in advance!
--
BestRegards
BlackSim
"Steven Sharp" <sharp@cadence.com> wrote in message
news:3a8e124e.0308251458.fd3d41b@posting.google.com...

asiandoof@hotmail.com (CupOfWater) wrote in message
news:<e0c9495d.0308251025.10e9e552@posting.google.com>...
Hi, I have some questions over the use of inout ports. Say I have a
closed source module (my_mod) that contains an 8 bit command i/o bus
declared as inout. Now in the module one level higher I'm trying to
communicate with F0. I'm using an 8 bit bus and an 8 bit register for
this purpose. I want any command written to the register to be
communicated to F0; and I want any command written out by F0 to be
available in the register. What kind of support does verilog have for
what I need?


now it appears that if I do:
io = 8'ha0;
then the module sees A0 on the bus and does some stuff. But I can't
seem to get a response from the module. From just what I have here,
do I have enough to do what I want to do?

As in real hardware, if you have multiple drivers of a bus, you will
need to have logic to determine which driver is active at any given
time. If multiple drivers are active at the same time, you will have
driver contention, which will prevent values from being transmitted
properly and can damage the hardware.

The most common way of inactivating a driver is to tristate it, putting
it into a Hi-Z state so that another driver can drive the bus. This
requires extra logic to determine which driver should be enabled. Then
you can set the driver to Hi-Z when not enabled, using the continuous
assignment (or bufif primitives).

assign stat_io = enable ? io : 8'hzz;

If you are synthesizing the design, this will only work if the technology
you are using supports tristating or some other mechanism for allowing
multiple drivers. Otherwise, you can't have a bidirectional bus.

It is a good idea to understand hardware before trying to write Verilog.