inout port instantiation in top level structural module

[kb33]

Hi,

If a port is defined as inout in an embedded module (see definition
and assignment below), then how should it be instantiated in the top
level structural module?

In the embedded module:
--------------------------------------

inout [`DATA_SZ-1:0] job_val;
reg [`DATA_SZ-1:0] curr_job_val,

assign job_val = (fsm_state == `SEND_VAL)? curr_job_val :
{`DATA_SZ{1'bz}};


In the top level structural module:
-----------------------------------------------
(When job_val is acting as an input to the embedded module, it gets
its value from the data_in input)

input [`DATA_SZ-1:0] data_in;
wire [`DATA_SZ-1:0] job_val;


job_module job_mod_top (....other I/O signals..
.job_val (data_in),
.
.
);


But this is obviously not working.
Thanks
Kanchan

 

On Sep 5, 1:22 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

Hi,

If a port is defined as inout in an embedded module (see definition
and assignment below), then how should it be instantiated in the top
level structural module?

In the embedded module:
--------------------------------------

inout [`DATA_SZ-1:0] job_val;
reg [`DATA_SZ-1:0] curr_job_val,

assign job_val = (fsm_state == `SEND_VAL)? curr_job_val :
{`DATA_SZ{1'bz}};

In the top level structural module:
-----------------------------------------------
(When job_val is acting as an input to the embedded module, it gets
its value from the data_in input)

input [`DATA_SZ-1:0] data_in;
wire [`DATA_SZ-1:0] job_val;

job_module job_mod_top (....other I/O signals..
.job_val (data_in),
.
.
);

But this is obviously not working.
Thanks
Kanchan

Hi,

data_in needs to be a reg in the top.
You should drive data_in when (fsm_state == `SEND_VAL) false

Daladois