Injecting glitch on bidirectional line

[ALuPin@web.de]

Hi,

I have two modules A,B connected at their serial bidirectional port.


entity tb_testscenario is
end tb_testscenario;

architecture arch_tb_testscenario of tb_testscenario is

component A
port( ...
Data_io : inout std_logic;
...
end component;

component B
port( ...
Data_io : inout std_logic;
...
end component;

signal t_data : std_logic;

begin

ut1 : A
port map ( ...
Data_io => t_data,
...
);

ut2 : B
port map ( ...
Data_io => t_data,
...
);

end arch_tb_testscenario;



Now I want a third module C to insert a glitch while the bus is driven
'Z'.

The port map of C in the toplevel is the following:

ut3: C
port map ( Clk_i => t_clk,
Ena_i => t_ena,
Data_io => t_data
);

The component itself looks like the following:

entity C is
port( Clk_i, Ena_i : in std_logic;
Data_io : inout std_logic
);
end C;

architecture arch_C of C is

begin

p_inject: process
begin
wait until Clk_i='1';
Data_io <= 'Z';

if Ena_i='1' then
Data_io <= '0';
end if;

end process p_inject;

end arch_C;

This approach works so far.


How can I insert the glitch while modules A or B are driving data on
the bidirectional line ?

Thank you for your opinion.

Rgds
Andre

 

[ALuPin@web.de]

Hi Kevin,

thank you for your answer.

If you try
to have C insert a glitch by say driving a '1' on to something that is being
driven by A or B to a '0' then all you'll get is 'X'...which probably isn't
terribly useful for inserting a fault.

Yes, I know. But it seems to be very tricky to describe that kind of
"resolve" function for
three members accessing the bidirectional line.

Andre

 

[KJ]

On Jul 11, 3:08 am, "ALu...@web.de" <ALu...@web.de> wrote:

Hi Kevin,

thank you for your answer.

If you try
to have C insert a glitch by say driving a '1' on to something that is being
driven by A or B to a '0' then all you'll get is 'X'...which probably isn't
terribly useful for inserting a fault.

Yes, I know. But it seems to be very tricky to describe that kind of
"resolve" function for
three members accessing the bidirectional line.

Andre

You've completely missed my point, you CAN'T put C on the same signal
as A and B. You have to break the connection and insert C in between
A and B. C therefore has a bi-directional interface to A and another
bi-directional interface to B, there will be no connection between A
and B. C has to be able to determine from the A/C and B/C connections
who is driving the signal and then copy the signals over to the other
side so that A and B each think they are talking to each other.

That's the way you need to model it.

KJ