Initializing memory to random numbers

M

--MMS--

Guest
Is it possible to initialize a memory (array) to random numbers, in
VHDL? Does anyone has an example that can post it?
Because I have initialized it to a fixed number, but random numbers
not yet.

One million thanks!
 
--MMS-- wrote:
Is it possible to initialize a memory (array) to random numbers, in
VHDL?
Click to expand...

Here's how I make a vhdl constant array with a function.
This one happens to be characters instead of vectors.

type char_file_t is file of character; -- one byte each
function spew(i_arg : integer) return char_array_t is
variable result : char_array_t(0 to i_arg-1);
variable index : char_index;
begin
for i in 0 to i_arg-1 loop
index := i mod (1+char_index'right);
result(i) := character'val(index);
end loop;
return result;
end function spew;
constant box_o_chars_c : char_array_t := spew(512);


You could do something similar with a vector array
and use a function like this for the data:

function randomize (arg_byte : char_t)
return char_t is
variable result_v : char_t;
begin
result_v := arg_byte; -- here it is
result_v := shift_left(result_v, 1); -- shift it
if (result_v(result_v'left)) = '1' then -- maybe invert mask
result_v := result_v xor mask_c;
end if;
return result_v;
end function randomize;

Good luck.

-- Mike Treseler
 
--MMS-- schrieb:
Is it possible to initialize a memory (array) to random numbers, in
VHDL? Does anyone has an example that can post it?
Click to expand...
What is the reason for it? For me this means pretty bad testability. If
an error occurs during development you can't find the reason if the
error depends on the data. What about building a set of random numbers
(using /dev/random or whatever), saving it to a file and using exactly
this set of numbers?

Ralf
 
Hmm.. I posted a reply here and I don't see it... it must have been an
error or something... anyway I will post it again:
-----------------

I thought that it was faster to initialize the array to random
numbers, but now that you tell me that, I see it is not the best
solution.

This is a simple memory controller I need to do for a course. They
suggested me to initialize the memory to see, in the simulation, if my
design is "doing" what it is supposed to do.

The thing is that my college background is not in Comp. Eng./ hardware
and this project has been somewhat harder for me.


Thank you for your comment,
MMS
-----------------------------------
On May 21, 11:07 am, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:
--MMS-- schrieb:

Is it possible to initialize a memory (array) to random numbers, in
VHDL? Does anyone has an example that can post it?

What is the reason for it? For me this means pretty bad testability. If
an error occurs during development you can't find the reason if the
error depends on the data. What about building a set of random numbers
(using /dev/random or whatever), saving it to a file and using exactly
this set of numbers?

Ralf
Click to expand...
 
On May 21, 10:07 am, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:
--MMS-- schrieb:

Is it possible to initialize a memory (array) to random numbers, in
VHDL? Does anyone has an example that can post it?

What is the reason for it? For me this means pretty bad testability. If
an error occurs during development you can't find the reason if the
error depends on the data. What about building a set of random numbers
(using /dev/random or whatever), saving it to a file and using exactly
this set of numbers?

Ralf
Click to expand...
If I can create a random set of vectors in vhdl, and do it the same
way every time, I'd rather do it in vhdl than a file.

But that's just me.

Andy
 
Andy schrieb:

If I can create a random set of vectors in vhdl, and do it the same
way every time, I'd rather do it in vhdl than a file.
Click to expand...
I agree. My point was that it would be preferable to use always the same
set of random numbers during development - or at least a set of numbers
that can be reproduced if one detects an error.

Ralf
 
Ralf Hildebrandt wrote:

Andy schrieb:

If I can create a random set of vectors in vhdl, and do it the same
way every time, I'd rather do it in vhdl than a file.

I agree. My point was that it would be preferable to use always the same
set of random numbers during development - or at least a set of numbers
that can be reproduced if one detects an error.
Click to expand...
If it needs to be (pseudo) random, but not necessarily PRBS, I always use
procedure ieee.math_real.uniform. It is easy to use (just need a wrapper to
scale to integers within the desired bonds) and it is very fast. It is also
repeatable, using the same start seed (one time initialisation).

See: http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#4.10
--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
THANKS!

--------------------------------------------------------------------------
On May 21, 10:58 am, Mike Treseler <mike_trese...@comcast.net> wrote:

> (...)
 
Mike Treseler wrote:


-- type char_file_t is file of character; -- one byte each
type char_array_t is array(natural range <>) of character;
function spew(i_arg : integer) return char_array_t is
variable result : char_array_t(0 to i_arg-1);
variable index : char_index;
begin
for i in 0 to i_arg-1 loop
index := i mod (1+char_index'right);
result(i) := character'val(index);
end loop;
return result;
end function spew;
constant box_o_chars_c : char_array_t := spew(512);
Click to expand...
D'oh!
I copied the wrong declaration above.

See
http://home.comcast.net/~mike_treseler/
for details.

-- Mike Treseler
 
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