Initializing memory from a testbench

R

rickman

Guest
I am testing a VHDL design using embedded CPU program memory which needs
to be initialized. The data to be stored in the RAM comes from an
external source and will be part of the configuration download in the
final system. During simulation, I can't seem to figure out how to
initialize it. I thought I might use the test bench to read the data
from a file, but I can't figure out how to access the memory since it
does not have an external interface. If I add logic to initialize the
memory from the test bench, this will be unused in the real chip and so
I will have a difference between my simulated chip and the real chip. I
prefer not to do that. I have been using an initial value on the memory
variable declaration, but the data changes as I work and this is very
clumsy.

I also saw an example using a shared variable with one process being the
normal memory model and the other being an init routine. But again,
this will use code that is only part of the simulation and should not be
there for the end device. I guess the code will not be synthesized, but
since it has to be in the target source and not the test bench, it will
either need to be removed or it will likely produce errors in synthesis.

Is there a way to directly access an internal signal or variable from a
test bench? I seem to recall doing this before, but it was a long time
ago and I may be getting a simulator command mixed up with VHDL.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
rickman wrote:

I am testing a VHDL design using embedded CPU program memory which needs
to be initialized. The data to be stored in the RAM comes from an
external source and will be part of the configuration download in the
final system. During simulation, I can't seem to figure out how to
initialize it.
Click to expand...
You might model the data block as a vhdl constant array of vectors.

-- Mike Treseler
 
Mike Treseler wrote:
rickman wrote:

I am testing a VHDL design using embedded CPU program memory which needs
to be initialized. The data to be stored in the RAM comes from an
external source and will be part of the configuration download in the
final system. During simulation, I can't seem to figure out how to
initialize it.

You might model the data block as a vhdl constant array of vectors.
Click to expand...
Thanks for the response, but the question is not how to declare the
signal or variable. That is not at issue. The question is how to
initialize the data in a way that does not require a recompliation of
the target code. Or better yet, no recompliation of the test bench
either, but rather reading the data from a file.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
"rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje
news:413F93AF.393AEDF0@yahoo.com...
I am testing a VHDL design using embedded CPU program memory which needs
to be initialized. The data to be stored in the RAM comes from an
external source and will be part of the configuration download in the
final system. During simulation, I can't seem to figure out how to
initialize it. I thought I might use the test bench to read the data
from a file, but I can't figure out how to access the memory since it
does not have an external interface. If I add logic to initialize the
memory from the test bench, this will be unused in the real chip and so
I will have a difference between my simulated chip and the real chip. I
prefer not to do that. I have been using an initial value on the memory
variable declaration, but the data changes as I work and this is very
clumsy.

I also saw an example using a shared variable with one process being the
normal memory model and the other being an init routine. But again,
this will use code that is only part of the simulation and should not be
there for the end device. I guess the code will not be synthesized, but
since it has to be in the target source and not the test bench, it will
either need to be removed or it will likely produce errors in synthesis.

Is there a way to directly access an internal signal or variable from a
test bench? I seem to recall doing this before, but it was a long time
ago and I may be getting a simulator command mixed up with VHDL.
Click to expand...

how about enclosing the initialisation part of the RAM (i guess you use a
function that reads a file) between the pragmas "synopsys synthesis_off" and
"synopsys synthesis_on"? (if you're initialising thru a function you should
avoid synthetising it too in the same way)

and as for accessing an internal signal, i know that you can "up" hierarchy
by specifiying it's full "pathname", but i dont know if it works "down"
hierarchy, you can always try.
 
"rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje
news:4140967F.2EF867B@yahoo.com...
roller wrote:

and as for accessing an internal signal, i know that you can "up"
hierarchy
by specifiying it's full "pathname", but i dont know if it works "down"
hierarchy, you can always try.

I was trying to do that, but I can't figure out the format for
specifying the heiarchy. I looked in the LRM and could not find any
references to that. What is used as separators in a "path" name?
Click to expand...
it's the dot like in Ada (and Java, or like "use work.package.all") though
it's been a long time since i read about it (plus i havent ever used it)
maybe you can check the visibility rules or tutorials explaining that, sorry
i couldnt help you more

http://tech-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#visibility
 
Mike Treseler wrote:
Alan wrote:

subtype wordT is std_logic_vector(15 downto 0); -- e.g.
type RomT is array (0 to 1023) of wordT;
constant MyRom : arrayT := FNFillRom("file name");

The advantage of this is that the ROM gets filled during elaboration,
and so is instantly available at time 0. The disadvantage is there's
no direct link to synthesis - unless I suppose you write the function
to read in the file in the format that your target technology
supports.

Another possible solution is to use perl or bash
to convert the external hex file to a deferred
constant package body something like:

constant MyRom : arrayT :=
(
-- begin data
x"0000",
x"0001",
x"0002",
x"0004",
x"0008",
x"0010",
x"0020",
x"0040"
-- ...
-- end data
);

This would give you synthsizable code,
but require running the script and
a "vcom myPackageBody.vhd" for
each iteration.
Click to expand...
This just might do the job. My only concern has to do with the fact
that my program memory is actually read/write, so the ram will have to
be initialized to this constant data. I don't know if the synthesis
tool can understand that this does not require two memories. :)


--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
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