Initializing inferred components with Xilinx ISE Foundation

[Matt Hardy]

Hello,

I have a large design implemented in Verilog. In the design there are
several thousand SRL16 type shift registers that are inferred from the
Verilog by XST. What is the best way to initialize each shift
register with different a unique value? Preferably this
initialization could be specified outside of the verilog so that
thousands or different module definitions are not needed. I also am
using all 96 block rams on the XC3S4000 and need to initialize those
as well.

Currently I am initializing the block rams in the module where they
are instantiated but for the final design I need this to be seperated
from the Verilog module definition because I don't want to have 96
different module definitions.

Thanks,
Matt Hardy

 

[Allan Herriman]

On 26 Oct 2003 23:23:14 -0800, google@matthardy.us (Matt Hardy) wrote:

Hello,

I have a large design implemented in Verilog. In the design there are
several thousand SRL16 type shift registers that are inferred from the
Verilog by XST. What is the best way to initialize each shift
register with different a unique value? Preferably this
initialization could be specified outside of the verilog so that
thousands or different module definitions are not needed. I also am
using all 96 block rams on the XC3S4000 and need to initialize those
as well.

Currently I am initializing the block rams in the module where they
are instantiated but for the final design I need this to be seperated
from the Verilog module definition because I don't want to have 96
different module definitions.

Can you figure out a way to specify the initial value using a
parameter? That way, you only need one module definition.

This is simple to do in VHDL, and ought to be possible in Verilog.

Regards,
Allan.