initialization of signals in design

[Johan Bernspĺng]

Hi,
I'm currently working on a core to a Microblaze system. It is a bridge
between the native OPB bus and a ISA bus interface. Since the ISA bus is
working with a clock frequency around 8 MHz I've divided the OPB clock (66
MHz) with 8 to obtain the bus clock signal. It works fine during simulation,
but when I try to use the clock signal as a trigger to ChipScope (logic
analyser) when everything is synthesized and downloaded to the FPGA, the
clock seem to be dead.
My guess is that it has to do with the initialization of the different
signals and counters utilized by the design. How do I write a process that
only runs once at start-up that sets all signals to desired values?

The clock divider looks as follows, is this an OK way to divide a clock?

if OPB_clk = '1' and clk_counter < 3 then
clk_counter <= clk_counter + 1;
elsif OPB_clk = '1' and clk_counter = 3 then
isa_clk <= not isa_clk;
clk_counter <= 0;
end if;

Regards

Johan

 

[fe]

"Johan Bernspĺng" <johan@itee.uq.edu.au> wrote in message
news:bo7hor$h9a$1@bunyip.cc.uq.edu.au...

Hi,
I'm currently working on a core to a Microblaze system. It is a bridge
between the native OPB bus and a ISA bus interface. Since the ISA bus is
working with a clock frequency around 8 MHz I've divided the OPB clock (66
MHz) with 8 to obtain the bus clock signal. It works fine during
simulation,
but when I try to use the clock signal as a trigger to ChipScope (logic
analyser) when everything is synthesized and downloaded to the FPGA, the
clock seem to be dead.
My guess is that it has to do with the initialization of the different
signals and counters utilized by the design. How do I write a process that
only runs once at start-up that sets all signals to desired values?

The clock divider looks as follows, is this an OK way to divide a clock?

if OPB_clk = '1' and clk_counter < 3 then
clk_counter <= clk_counter + 1;
elsif OPB_clk = '1' and clk_counter = 3 then
isa_clk <= not isa_clk;
clk_counter <= 0;
end if;

Regards

Johan

No, you must use the clocked process template (dff) to create a counter.

something like this:

ps_isa_clk : process (i_rst_an, OPB_clk)
variable v_cnt_q : unsigned(2 downto 0);
begin
if i_rst_an = '0' then
v_cnt_q := (others => '0');
elsif rising_edge(OPB_clk) then
v_cnt_q := v_cnt_q + 1;
end if;
isa_clk <= v_cnt_q(2);
end process;

regards
fe