Initialization of arrays

How does one initialize 'nibbles' in the same way as 'bigreg' is
initialised .. ? (verilog)

reg [1023:0] bigreg =
576'h555555555555555D00014AB7AE08002143658709800054;
reg [3:0] nibbles[0:256];

(Enviroment is Xilinx/Linux ISE xst)

I prefer a vendor neutral way.. but if it's not possible tweaks are
ok

 

On Dec 28 2007, 5:22 am, posedg...@yahoo.com wrote:

How does one initialize 'nibbles' in the same way as 'bigreg' is
initialised .. ?  (verilog)

reg [1023:0]    bigreg > 576'h555555555555555D00014AB7AE08002143658709800054;
reg [3:0]       nibbles[0:256];

Since Verilog does not support assigning an entire array in one
assignment statement, nor a way of representing a constant of array
type (which would be useless without operations like assignments of
entire arrays anyway), there is no way to do this with an initializer
in Verilog. You would have to use an initial block with 257
assignments to the individual elements, or perhaps a loop if there is
a regular pattern to the values, or $readmem from a data file.

SystemVerilog does support array assignments and constants of array
type, so it does allow this.

Note that any of these initialization mechanisms may be non-
synthesizable.

 

[gabor]

On Jan 2, 11:12 am, sh...@cadence.com wrote:

On Dec 28 2007, 5:22 am, posedg...@yahoo.com wrote:

How does one initialize 'nibbles' in the same way as 'bigreg' is
initialised .. ? (verilog)

reg [1023:0] bigreg =
576'h555555555555555D00014AB7AE08002143658709800054;
reg [3:0] nibbles[0:256];

Since Verilog does not support assigning an entire array in one
assignment statement, nor a way of representing a constant of array
type (which would be useless without operations like assignments of
entire arrays anyway), there is no way to do this with an initializer
in Verilog. You would have to use an initial block with 257
assignments to the individual elements, or perhaps a loop if there is
a regular pattern to the values, or $readmem from a data file.

SystemVerilog does support array assignments and constants of array
type, so it does allow this.

Note that any of these initialization mechanisms may be non-
synthesizable.

The usual method is to place the initialization values in a file
and use $readmemh to initialize in one statement. Although
this is "vendor neutral" in the sense that it uses only
Verilog constructs, whether it is synthesizable depends on
the synthesis vendor. Newer versions of XST, for example
allow initialization using $readmemh in an initial block.