Initialization of a Xilinx RAM Core in a simulation

[Thomas Fuchs]

Hello,

I want to initialize a Xilinx RAM Core for my simulation with ModelSim.
For this purpose I generated a MyRAM.mif file for the RAM (with the
ISE). I also copied this file in my ModelSim simulation folder.
I can see in the MyRAM.vhd wrapper file the generic "c_mem_init_file =>
MyRAM.mif".
I hoped this would be enough but it's not because I get undefined ("X")
data out of the RAM.
Can somesody help me?
Thank you.

Thomas Fuchs

 

[Mike Treseler]

Thomas Fuchs wrote:

Hello,

I want to initialize a Xilinx RAM Core for my simulation with ModelSim.

http://groups.google.com/groups?q=vhdl+ram+data+initialization+rom