Initialising a signal

[jan]

Hello all,

Is there a difference between:

architecture b of e is
signal mysig: std_logic := '0';
begin
...
end architecture b;

AND,

architecture b of e is
signal mysig: std_logic;
begin
mysig <= '0';
...
end architecture b;
?

Thanks in advance.

--
Jacques Viviers

 

[valentin tihomirov]

architecture b of e is
signal mysig: std_logic := '0';
begin
...
end architecture b;
simulation shows you constant '0', systesys will result in undefined output

architecture b of e is
signal mysig: std_logic;
begin
mysig <= '0';
...
end architecture b;
both syth and sim give you '0'.

 

[jan]

valentin tihomirov wrote:

architecture b of e is
signal mysig: std_logic := '0';
begin
...
end architecture b;

simulation shows you constant '0', systesys will result in undefined output

architecture b of e is
signal mysig: std_logic;
begin
mysig <= '0';
...
end architecture b;

both syth and sim give you '0'.


Thanks, I have been porting some Verilog, and had lots of

wire mywire = 1'b0;
but Verilog doesn't have a seperate declaration area...
I have translated this like the second example above.
I am glad to see it is the better choice.

--
JV

 

[David Jones]

In article <brn55b$b4j$1@ctb-nnrp2.saix.net>,
jan <jviviers@NOsPam.cs.up.ac.za> wrote:

Hello all,

Is there a difference between:

architecture b of e is
signal mysig: std_logic := '0';
begin
...
end architecture b;

AND,

architecture b of e is
signal mysig: std_logic;
begin
mysig <= '0';
...
end architecture b;

Yup.

At time zero, mysig in the first architecture will have value '0'.
For the second, it will have 'U' for a delta delay, at which point
the assignment to '0' will take effect.

For ASIC synthesis, the initialization to '0' might get kicked out
in the first architecture, while you are tying to ground in the
second.

FPGAs that feature initialization without reset will tolerate the
initial value in the first case. Still not recommended, though.