Initialisation of two dimensional array to known non-zero va

K

K. Sudheer Kumar

Guest
To declare and initialise a one-bit register in verilog we use the
following statement
reg one_bit_reg=1'b0;

Similarly, to declare and initialise a one dimension reg (e.g. 8-bit)
we can write
reg [7:0] reg_len_8=8'd0;

We can declare a two dimensional array (e.g. 16x8-bit) as
reg [7:0] reg_dim_2 [15:0];

But how can we initialise this array in the same statement?
or How do we declare the initial state (known non-zero values) of an
array without using extra logic (especially when implementing on
hardware (FPGAs))?
 
The eg [7:0] reg_len_8=8'd0; statement is not synthesizable.
use asyncronous reset. It will use built-in FFs with asyncronous set/
reset.

always @(posedge clk or posedge arst)
if(arst) begin
reg_dim_2[0] <= ....;
reg_dim_2[1] <= ....;
reg_dim_2[2] <= ....;
etc
reg_dim_2[15] <= ....;
end else begin
Your Logic here
end
 
On Jan 31, 5:26 am, "Michael" <michae...@gmail.com> wrote:
reg_len_8=8'd0; statement is not synthesizable.
use asyncronous reset. It will use built-in FFs with asyncronous set/
reset.

always @(posedge clk or posedge arst)
if(arst) begin
reg_dim_2[0] <= ....;
reg_dim_2[1] <= ....;
reg_dim_2[2] <= ....;
etc
reg_dim_2[15] <= ....;
end else begin
Your Logic here
end

This would certainly work, but it usually results in the use of fabric
flip-flops
rather than distributed or block memory. I would guess that comes
into
the category of "using extra logic" in an FPGA. If you want the array
initialized only when the bitstream is loaded and don't need a real
asynchronous reset at some later time, you could use distributed or
block memory for the array. I've generally found that the synthesis
tools are not very good at inferring initialized memory, and generally
you need to look up how to do it for your combination of FPGA
vendor and tools. I generally prefer to instantiate the "ROM",
but I also don't generally create one design for multiple target
types. I would suggest using $readmemh to initialize the array
from a file, but I'm not sure what synthesis tools will allow this
method.

HTH,
Gabor
 

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