initialiazation of memory during reset

[ybhanu020@gmail.com]

Is the below code is properly coded during reset during synthesis how it will be synthesis?

always@(posedge clk,negedge reset)begin
if(!reset)begin
conv_mat_out_flag<=0;
for(x=0;x<11;x=x+1)begin
H_real[x] <= 0;
H_imag[x] <= 0;
end
end

 

[GaborSzakacs]

ybhanu020@gmail.com wrote:

Is the below code is properly coded during reset during synthesis how it will be synthesis?

always@(posedge clk,negedge reset)begin
if(!reset)begin
conv_mat_out_flag<=0;
for(x=0;x<11;x=x+1)begin
H_real[x] <= 0;
H_imag[x] <= 0;
end
end

Assuming there was an else for the "if (!reset)" then this
should synthesize into 12 registers that get asynchronously
reset when your "reset" signal is low. Without the else
clause this would just get optimised away to all zero.

In no case would this synthesize into a "memory" of the
sort that you might have in the distributed or block
RAM of an FPGA. That's because memories don't typically
have the ability to reset the entire array at once, whether
synchronous or asynchronous.

--
Gabor