Initial value

[Borge]

I'm looking for a way to synthesize verilog code with a fixed startup
value in a register. I asked some Xilinx people, but they only knew it
for VHDL. Is there a way to translate this to Verilog? May I use
"initial" statements in synthesizeable code?

His VHDL example says:

entity xyz()
end entity
architecture
signal cnt:std_logic_vector(7..0):=0xFF
begin


Thanks,
Břrge

 

[Jonathan Bromley]

On 17 Nov 2006 02:42:28 -0800, "Borge" <borge.strand@gmail.com> wrote:

I'm looking for a way to synthesize verilog code with a fixed startup
value in a register. I asked some Xilinx people, but they only knew it
for VHDL. Is there a way to translate this to Verilog? May I use
"initial" statements in synthesizeable code?

His VHDL example says:

entity xyz()
end entity
architecture
signal cnt:std_logic_vector(7..0):=0xFF

I think that'll be ... := X"FF";

In Verilog you can initialise a variable thus:

module (...);

reg [7:0] Flipflop;

initial Flipflop = 8'hFF;
always @(posedge clock)
Flipflop <= some_new_value;

But I'm not sure whether XST will synthesise this. Even the VHDL
signal initialisation is unusual for synthesis; XST accepts it, but
many tools don't. In Verilog it's even more troublesome because
in effect you have two separate processes writing to the same
variable, and in any other context that would be unacceptable
for synthesis.

An alternative approach is to give the signal an asynchronous
reset, and then to tie-off that reset false:

always @(posedge clock or posedge dummy_reset)
if (reset)
Flipflop <= 8'hFF:
else // clocked action
Flipflop <= some_new_value;

Somewhere at the top level, tie-off signal "dummy_reset" to
false. I think you'll find that XST will use this as a hint to
set the power-up value of the register.

Alternatively, it's easy enough to do this in the Xilinx
constraints file.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[John_H]

Borge wrote:

I'm looking for a way to synthesize verilog code with a fixed startup
value in a register. I asked some Xilinx people, but they only knew it
for VHDL. Is there a way to translate this to Verilog? May I use
"initial" statements in synthesizeable code?

His VHDL example says:

entity xyz()
end entity
architecture
signal cnt:std_logic_vector(7..0):=0xFF
begin


Thanks,
Břrge

XST does initial values.
Synplicity still doesn't but hopes are that they will some month soon.

A slight alternative to Jonathon Bromley's suggestion of:

reg [7:0] Flipflop;

initial Flipflop = 8'hFF;
always @(posedge clock)
Flipflop <= some_new_value;

leverages the Verilog register initialization syntax:

reg [7:0] Flipflop = 8'hFF;
always @(posedge clock)
Flipflop <= some_new_value;

I _so_ look forward to the day I can use my "high end" synthesis tool to
do what the "low end" tools have been doing for a while. Even the
respectable free Verilog synthesizer - Icarus Verilog - supports the
register initialization.

- John_H

 

[Jonathan Bromley]

On Fri, 17 Nov 2006 13:23:52 GMT, John_H
<newsgroup@johnhandwork.com> wrote:

A slight alternative to Jonathon Bromley's suggestion of:

reg [7:0] Flipflop;

initial Flipflop = 8'hFF;
always @(posedge clock)
Flipflop <= some_new_value;

leverages the Verilog register initialization syntax:

reg [7:0] Flipflop = 8'hFF;
always @(posedge clock)
Flipflop <= some_new_value;

Yes - probably a better hint to tools about what you're trying
to do, as well.

However, I generally try to avoid that because it reminds me
too much of VHDL initialisation; and (at least in Verilog as
opposed to SystemVerilog) the declaration/initialisation
syntax is NOT the same as VHDL's; it is defined to be
exactly equivalent to the declaration and an initial
block that does the initialisation. That has some
entertaining side-effects relating to time 0 races.
Even though this is unlikely to be a problem for
clocked logic, I still don't like the silent subtlety.

[By the way: apologies for the mismatch between
John's initialization and my initialisation. The UK
spelling is in my blood; too late to change now!]
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Borge]

Thanks for your help here guys! I'm using the code to write an internal
reset signal generator, something like this:

reg reset_local = 1'b1;
reg[7:0] counter = 4'hF;
always @(posedge clock)
begin
if (counter == 4'h8)
reset_local <= 1'b0;
if (counter == 4'b2)
reset_local <= 1'b1;
if (counter != 4'h0)
counter <= counter -1;
end

Makes sense?


Thanks,
Břrge

Jonathan Bromley wrote:

On Fri, 17 Nov 2006 13:23:52 GMT, John_H
newsgroup@johnhandwork.com> wrote:


A slight alternative to Jonathon Bromley's suggestion of:
leverages the Verilog register initialization syntax:

reg [7:0] Flipflop = 8'hFF;
always @(posedge clock)
Flipflop <= some_new_value;

Yes - probably a better hint to tools about what you're trying
to do, as well.

However, I generally try to avoid that because it reminds me
too much of VHDL initialisation; and (at least in Verilog as
opposed to SystemVerilog) the declaration/initialisation
syntax is NOT the same as VHDL's; it is defined to be
exactly equivalent to the declaration and an initial
block that does the initialisation. That has some
entertaining side-effects relating to time 0 races.
Even though this is unlikely to be a problem for
clocked logic, I still don't like the silent subtlety.